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Andrew W
2022-08-28 16:12:16 -05:00
parent 5a2894ed1b
commit 7dabaef6f6
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93
EE203/Noah Woodlee/Decoder/output_files/decoder.asm.rpt Normal file
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Assembler report for decoder
Thu Jan 21 20:01:57 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Jan 21 20:01:57 2021 ;
; Revision Name ; decoder ;
; Top-level Entity Name ; decoder ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C7G ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+------------------------------------------------------------------------+
; Assembler Generated Files ;
+------------------------------------------------------------------------+
; File Name ;
+------------------------------------------------------------------------+
; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof ;
+------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.sof ;
+----------------+---------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------------------------------+
; Device ; 10M50DAF484C7G ;
; JTAG usercode ; 0x0026FF7D ;
; Checksum ; 0x0026FF7D ;
+----------------+---------------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Processing started: Thu Jan 21 20:01:55 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4685 megabytes
Info: Processing ended: Thu Jan 21 20:01:57 2021
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02

1
EE203/Noah Woodlee/Decoder/output_files/decoder.done Normal file
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Thu Jan 21 20:02:01 2021

108
EE203/Noah Woodlee/Decoder/output_files/decoder.eda.rpt Normal file
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EDA Netlist Writer report for decoder
Thu Jan 21 20:12:11 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Thu Jan 21 20:12:11 2021 ;
; Revision Name ; decoder ;
; Top-level Entity Name ; decoder ;
; Family ; MAX 10 ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name ; ModelSim-Altera (Verilog) ;
; Generate functional simulation netlist ; On ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+---------------------------+
+---------------------------------------------------------------------------+
; Simulation Generated Files ;
+---------------------------------------------------------------------------+
; Generated Files ;
+---------------------------------------------------------------------------+
; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//decoder.vo ;
+---------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Intel and sold by Intel or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Thu Jan 21 20:12:11 2021
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file decoder.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4641 megabytes
Info: Processing ended: Thu Jan 21 20:12:11 2021
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

1215
EE203/Noah Woodlee/Decoder/output_files/decoder.fit.rpt Normal file
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File diff suppressed because it is too large Load Diff

8
EE203/Noah Woodlee/Decoder/output_files/decoder.fit.smsg Normal file
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Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

18
EE203/Noah Woodlee/Decoder/output_files/decoder.fit.summary Normal file
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Fitter Status : Successful - Thu Jan 21 20:01:54 2021
Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Revision Name : decoder
Top-level Entity Name : decoder
Family : MAX 10
Device : 10M50DAF484C7G
Timing Models : Final
Total logic elements : 5 / 49,760 ( < 1 % )
Total combinational functions : 5 / 49,760 ( < 1 % )
Dedicated logic registers : 0 / 49,760 ( 0 % )
Total registers : 0
Total pins : 6 / 360 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 1,677,312 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
UFM blocks : 0 / 1 ( 0 % )
ADC blocks : 0 / 2 ( 0 % )

137
EE203/Noah Woodlee/Decoder/output_files/decoder.flow.rpt Normal file
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Flow report for decoder
Thu Jan 21 20:12:11 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Jan 21 20:12:11 2021 ;
; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Revision Name ; decoder ;
; Top-level Entity Name ; decoder ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C7G ;
; Timing Models ; Final ;
; Total logic elements ; 5 / 49,760 ( < 1 % ) ;
; Total combinational functions ; 5 / 49,760 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 6 / 360 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 1,677,312 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 01/21/2021 20:01:41 ;
; Main task ; Compilation ;
; Revision Name ; decoder ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 189559947077153.161128090107632 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 4788 MB ; 00:00:16 ;
; Fitter ; 00:00:06 ; 1.0 ; 5902 MB ; 00:00:08 ;
; Assembler ; 00:00:02 ; 1.0 ; 4685 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4872 MB ; 00:00:02 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4632 MB ; 00:00:00 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4641 MB ; 00:00:00 ;
; Total ; 00:00:18 ; -- ; -- ; 00:00:28 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+-----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; TimeQuest Timing Analyzer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; ENG227-02 ; Windows 10 ; 10.0 ; x86_64 ;
+---------------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder
quartus_fit --read_settings_files=off --write_settings_files=off decoder -c decoder
quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder
quartus_sta decoder -c decoder
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder

8
EE203/Noah Woodlee/Decoder/output_files/decoder.jdi Normal file
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<sld_project_info>
<project>
<hash md5_digest_80b="0c72437d6d88147662ca"/>
</project>
<file_info>
<file device="10M50DAF484C7G" path="decoder.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

284
EE203/Noah Woodlee/Decoder/output_files/decoder.map.rpt Normal file
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Analysis & Synthesis report for decoder
Thu Jan 21 20:01:47 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Post-Synthesis Netlist Statistics for Top Partition
10. Elapsed Time Per Partition
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Jan 21 20:01:47 2021 ;
; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Revision Name ; decoder ;
; Top-level Entity Name ; decoder ;
; Family ; MAX 10 ;
; Total logic elements ; 4 ;
; Total combinational functions ; 4 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 6 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; UFM blocks ; 0 ;
; ADC blocks ; 0 ;
+------------------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 10M50DAF484C7G ; ;
; Top-level entity name ; decoder ; decoder ;
; Family name ; MAX 10 ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; OpenCore Plus hardware evaluation ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 8 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+
; decoder.bdf ; yes ; User Block Diagram/Schematic File ; C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf ; ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+---------+
+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
; Estimated Total logic elements ; 4 ;
; ; ;
; Total combinational functions ; 4 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 4 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 4 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 6 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; B~input ;
; Maximum fan-out ; 4 ;
; Total fan-out ; 18 ;
; Average fan-out ; 1.13 ;
+---------------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
; |decoder ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; |decoder ; decoder ; work ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 6 ;
; cycloneiii_lcell_comb ; 5 ;
; normal ; 5 ;
; 1 data inputs ; 1 ;
; 2 data inputs ; 4 ;
; ; ;
; Max LUT depth ; 2.00 ;
; Average LUT depth ; 1.57 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Processing started: Thu Jan 21 20:01:40 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file decoder.bdf
Info (12023): Found entity 1: decoder
Info (12127): Elaborating entity "decoder" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 10 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 4 output pins
Info (21061): Implemented 4 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4788 megabytes
Info: Processing ended: Thu Jan 21 20:01:47 2021
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:16

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Analysis & Synthesis Status : Successful - Thu Jan 21 20:01:47 2021
Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Revision Name : decoder
Top-level Entity Name : decoder
Family : MAX 10
Total logic elements : 4
Total combinational functions : 4
Dedicated logic registers : 0
Total registers : 0
Total pins : 6
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0
UFM blocks : 0
ADC blocks : 0

556
EE203/Noah Woodlee/Decoder/output_files/decoder.pin Normal file
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-- Copyright (C) 2016 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Intel and sold by Intel or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1A: 2.5V
-- Bank 1B: 2.5V
-- Bank 2: 2.5V
-- Bank 3: 2.5V
-- Bank 4: 2.5V
-- Bank 5: 2.5V
-- Bank 6: 2.5V
-- Bank 7: 2.5V
-- Bank 8: 2.5V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
CHIP "decoder" ASSIGNED TO AN: 10M50DAF484C7G
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 :
GND : A22 : gnd : : : :
Q1 : AA1 : output : 2.5 V : : 3 : N
Q2 : AA2 : output : 2.5 V : : 3 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 :
GND : AA4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
GND : AA18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
GND : AB1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
GND : AB22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 :
GND : B6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 :
GND : B9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 :
GND : B13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
GND : B18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B :
GND : D4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
GND : D11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
GND : D16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 :
GND : D20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B :
GND : E2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A :
NC : E5 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 :
GND : E7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A :
NC : F6 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N
VCCIO8 : F9 : power : : 2.5V : 8 :
GND : F10 : gnd : : : :
VCCIO8 : F11 : power : : 2.5V : 8 :
VCCIO7 : F12 : power : : 2.5V : 7 :
GND : F13 : gnd : : : :
VCCIO7 : F14 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B :
~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A :
ANAIN1 : G5 : : : : :
GND : G6 : gnd : : : :
VCCD_PLL3 : G7 : power : : 1.2V : :
GND : G8 : gnd : : : :
~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N
VCCIO8 : G10 : power : : 2.5V : 8 :
VCCIO8 : G11 : power : : 2.5V : 8 :
VCCIO7 : G12 : power : : 2.5V : 7 :
VCCIO7 : G13 : power : : 2.5V : 7 :
VCCIO7 : G14 : power : : 2.5V : 7 :
GND : G15 : gnd : : : :
VCCD_PLL2 : G16 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 :
GND : G18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 :
GND : G21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B :
~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A :
REFGND : H5 : : : : :
ADC_VREF : H6 : : : : :
VCCA_ADC : H7 : power : : 2.5V : :
VCCA3 : H8 : power : : 2.5V : :
~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N
~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 :
VCCA2 : H15 : power : : 2.5V : :
VCCIO6 : H16 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B :
GND : J2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A :
ANAIN2 : J5 : : : : :
GND : J6 : gnd : : : :
VCCINT : J7 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 :
GND : J16 : gnd : : : :
VCCIO6 : J17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 :
GND : J19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B :
GND : K3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A :
VCCIO1A : K7 : power : : 2.5V : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B :
GND : K10 : gnd : : : :
VCC : K11 : power : : 1.2V : :
GND : K12 : gnd : : : :
VCC : K13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 :
VCCIO6 : K16 : power : : 2.5V : 6 :
VCCIO6 : K17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B :
DNU : L3 : : : : :
~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N
GND : L5 : gnd : : : :
VCCIO1A : L6 : power : : 2.5V : 1A :
VCCIO1B : L7 : power : : 2.5V : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B :
VCC : L10 : power : : 1.2V : :
VCC : L11 : power : : 1.2V : :
VCC : L12 : power : : 1.2V : :
GND : L13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 :
VCCIO6 : L16 : power : : 2.5V : 6 :
GND : L17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 :
GND : L21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B :
~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N
VCCIO1B : M6 : power : : 2.5V : 1B :
GND : M7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 :
GND : M10 : gnd : : : :
VCC : M11 : power : : 1.2V : :
VCC : M12 : power : : 1.2V : :
VCC : M13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 :
GND : M16 : gnd : : : :
VCCIO6 : M17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 :
GND : M19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 :
VCCIO2 : N6 : power : : 2.5V : 2 :
VCCIO2 : N7 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 :
VCC : N10 : power : : 1.2V : :
GND : N11 : gnd : : : :
VCC : N12 : power : : 1.2V : :
GND : N13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 :
VCCIO5 : N16 : power : : 2.5V : 5 :
VCCIO6 : N17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 :
GND : P2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 :
GND : P6 : gnd : : : :
VCCIO2 : P7 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 :
VCCIO5 : P16 : power : : 2.5V : 5 :
GND : P17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
VCCIO2 : R6 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
VCCA1 : R8 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 :
VCCIO5 : R16 : power : : 2.5V : 5 :
VCCIO5 : R17 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 :
GND : R19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 :
GND : R21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
GND : T4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 :
VCCD_PLL1 : T7 : power : : 1.2V : :
GND : T8 : gnd : : : :
VCCIO3 : T9 : power : : 2.5V : 3 :
VCCIO3 : T10 : power : : 2.5V : 3 :
VCCIO3 : T11 : power : : 2.5V : 3 :
VCCIO4 : T12 : power : : 2.5V : 4 :
VCCIO4 : T13 : power : : 2.5V : 4 :
GND : T14 : gnd : : : :
VCCA4 : T15 : power : : 2.5V : :
GND : T16 : gnd : : : :
VCCIO5 : T17 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 :
Q3 : U7 : output : 2.5 V : : 3 : N
VCCIO3 : U8 : power : : 2.5V : 3 :
VCCIO3 : U9 : power : : 2.5V : 3 :
GND : U10 : gnd : : : :
VCCIO4 : U11 : power : : 2.5V : 4 :
VCCIO4 : U12 : power : : 2.5V : 4 :
GND : U13 : gnd : : : :
VCCIO4 : U14 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 :
VCCD_PLL4 : U16 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
GND : V2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 :
GND : V6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 :
GND : V19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
B : W3 : input : 2.5 V : : 3 : N
A : W4 : input : 2.5 V : : 3 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 :
GND : W21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 :
Q0 : Y2 : output : 2.5 V : : 3 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 :
GND : Y9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 :
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 :
GND : Y15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :

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TimeQuest Timing Analyzer report for decoder
Thu Jan 21 20:02:01 2021
Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1200mV 85C Model Fmax Summary
6. Slow 1200mV 85C Model Setup Summary
7. Slow 1200mV 85C Model Hold Summary
8. Slow 1200mV 85C Model Recovery Summary
9. Slow 1200mV 85C Model Removal Summary
10. Slow 1200mV 85C Model Minimum Pulse Width Summary
11. Slow 1200mV 85C Model Metastability Summary
12. Slow 1200mV 0C Model Fmax Summary
13. Slow 1200mV 0C Model Setup Summary
14. Slow 1200mV 0C Model Hold Summary
15. Slow 1200mV 0C Model Recovery Summary
16. Slow 1200mV 0C Model Removal Summary
17. Slow 1200mV 0C Model Minimum Pulse Width Summary
18. Slow 1200mV 0C Model Metastability Summary
19. Fast 1200mV 0C Model Setup Summary
20. Fast 1200mV 0C Model Hold Summary
21. Fast 1200mV 0C Model Recovery Summary
22. Fast 1200mV 0C Model Removal Summary
23. Fast 1200mV 0C Model Minimum Pulse Width Summary
24. Fast 1200mV 0C Model Metastability Summary
25. Multicorner Timing Analysis Summary
26. Board Trace Model Assignments
27. Input Transition Times
28. Signal Integrity Metrics (Slow 1200mv 0c Model)
29. Signal Integrity Metrics (Slow 1200mv 85c Model)
30. Signal Integrity Metrics (Fast 1200mv 0c Model)
31. Clock Transfers
32. Report TCCS
33. Report RSKM
34. Unconstrained Paths Summary
35. Unconstrained Input Ports
36. Unconstrained Output Ports
37. Unconstrained Input Ports
38. Unconstrained Output Ports
39. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-----------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Timing Analyzer ; TimeQuest ;
; Revision Name ; decoder ;
; Device Family ; MAX 10 ;
; Device Name ; 10M50DAF484C7G ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 8 ;
; ; ;
; Average used ; 1.01 ;
; Maximum used ; 8 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-8 ; 0.2% ;
+----------------------------+-------------+
----------
; Clocks ;
----------
No clocks to report.
--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Q0 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; Q1 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; Q2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; Q3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+---------------------------------------------------------------------------------+
; Input Transition Times ;
+---------------------+-----------------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------------+-----------------------+-----------------+-----------------+
; B ; 2.5 V ; 2000 ps ; 2000 ps ;
; A ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
+---------------------+-----------------------+-----------------+-----------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0859 V ; 0.289 V ; 0.136 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ; 2.32 V ; 8.25e-09 V ; 2.41 V ; -0.0871 V ; 0.291 V ; 0.138 V ; 3.15e-10 s ; 4.16e-10 s ; No ; Yes ;
; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ; 2.32 V ; 8.26e-09 V ; 2.4 V ; -0.0773 V ; 0.156 V ; 0.166 V ; 4.55e-10 s ; 4.33e-10 s ; No ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ; 2.32 V ; 1.39e-08 V ; 2.39 V ; -0.0409 V ; 0.21 V ; 0.121 V ; 4.7e-10 s ; 5.93e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ;
; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.049 V ; 0.154 V ; 0.186 V ; 4.63e-10 s ; 4.5e-10 s ; Yes ; Yes ;
; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0508 V ; 0.153 V ; 0.187 V ; 4.63e-10 s ; 4.49e-10 s ; Yes ; Yes ;
; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ; 2.32 V ; 1.16e-06 V ; 2.37 V ; -0.0449 V ; 0.201 V ; 0.093 V ; 4.89e-10 s ; 5.81e-10 s ; Yes ; No ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ; 2.32 V ; 1.97e-06 V ; 2.36 V ; -0.0173 V ; 0.144 V ; 0.094 V ; 6.44e-10 s ; 7.2e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Q0 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; Q1 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; Q2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; Q3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.77 V ; -0.0486 V ; 0.285 V ; 0.06 V ; 2.8e-10 s ; 3.04e-10 s ; No ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 2 ; 2 ;
; Unconstrained Input Port Paths ; 8 ; 8 ;
; Unconstrained Output Ports ; 4 ; 4 ;
; Unconstrained Output Port Paths ; 8 ; 8 ;
+---------------------------------+-------+------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; Q0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; Q0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; Q3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Processing started: Thu Jan 21 20:01:58 2021
Info: Command: quartus_sta decoder -c decoder
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1200mV 85C Model
Info (332140): No fmax paths to report
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1200mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 4872 megabytes
Info: Processing ended: Thu Jan 21 20:02:01 2021
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02

5
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------------------------------------------------------------
TimeQuest Timing Analyzer Summary
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