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Andrew W
2022-08-28 16:12:16 -05:00
parent 5a2894ed1b
commit 7dabaef6f6
2345 changed files with 1343530 additions and 0 deletions
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80
EE203/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt Normal file
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// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "01/21/2021 20:12:10"
// Verilog Test Bench (with test vectors) for design : decoder
//
// Simulation tool : 3rd Party
//
`timescale 1 ps/ 1 ps
module decoder_vlg_vec_tst();
// constants
// general purpose registers
reg A;
reg B;
// wires
wire Q0;
wire Q1;
wire Q2;
wire Q3;
// assign statements (if any)
decoder i1 (
// port map - connection between master ports and signals/registers
.A(A),
.B(B),
.Q0(Q0),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3)
);
initial
begin
#200000 $finish;
end
// A
initial
begin
A = 1'b0;
A = #10000 1'b1;
A = #20000 1'b0;
A = #30000 1'b1;
A = #30000 1'b0;
A = #60000 1'b1;
A = #10000 1'b0;
end
// B
initial
begin
B = 1'b0;
B = #60000 1'b1;
B = #30000 1'b0;
B = #20000 1'b1;
B = #10000 1'b0;
B = #30000 1'b1;
B = #10000 1'b0;
end
endmodule

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EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.do Normal file
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onerror {exit -code 1}
vlib work
vlog -work work decoder.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst
vcd file -direction decoder.msim.vcd
vcd add -internal decoder_vlg_vec_tst/*
vcd add -internal decoder_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f

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EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.msim.vcd Normal file
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$comment
File created using the following command:
vcd file decoder.msim.vcd -direction
$end
$date
Thu Jan 21 20:12:12 2021
$end
$version
ModelSim Version 10.5b
$end
$timescale
1ps
$end
$scope module decoder_vlg_vec_tst $end
$var reg 1 ! A $end
$var reg 1 " B $end
$var wire 1 # Q0 $end
$var wire 1 $ Q1 $end
$var wire 1 % Q2 $end
$var wire 1 & Q3 $end
$scope module i1 $end
$var wire 1 ' gnd $end
$var wire 1 ( vcc $end
$var wire 1 ) unknown $end
$var tri1 1 * devclrn $end
$var tri1 1 + devpor $end
$var tri1 1 , devoe $end
$var wire 1 - ~QUARTUS_CREATED_GND~I_combout $end
$var wire 1 . ~QUARTUS_CREATED_UNVM~~busy $end
$var wire 1 / ~QUARTUS_CREATED_ADC1~~eoc $end
$var wire 1 0 ~QUARTUS_CREATED_ADC2~~eoc $end
$var wire 1 1 Q0~output_o $end
$var wire 1 2 Q1~output_o $end
$var wire 1 3 Q2~output_o $end
$var wire 1 4 Q3~output_o $end
$var wire 1 5 B~input_o $end
$var wire 1 6 A~input_o $end
$var wire 1 7 inst~combout $end
$var wire 1 8 inst2~0_combout $end
$var wire 1 9 inst2~1_combout $end
$var wire 1 : inst2~2_combout $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0!
0"
1#
0$
0%
0&
0'
1(
x)
1*
1+
1,
0-
z.
z/
z0
11
02
03
04
05
06
07
08
09
0:
$end
#10000
1!
16
17
19
13
01
0#
1%
#30000
0!
06
07
09
03
11
1#
0%
#60000
1"
1!
16
15
17
1:
14
01
0#
1&
#90000
0"
0!
06
05
07
0:
04
11
1#
0&
#110000
1"
15
17
18
12
01
0#
1$
#120000
0"
05
07
08
02
11
1#
0$
#150000
1!
1"
15
16
17
1:
14
01
0#
1&
#160000
0!
0"
05
06
07
0:
04
11
1#
0&
#200000

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EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.sft Normal file
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set tool_name "ModelSim-Altera (Verilog)"

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EE203/Noah Woodlee/Decoder/simulation/qsim/decoder.vo Normal file
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// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition"
// DATE "01/21/2021 20:12:11"
//
// Device: Altera 10M50DAF484C7G Package FBGA484
//
//
// This Verilog file should be used for ModelSim-Altera (Verilog) only
//
`timescale 1 ps/ 1 ps
module decoder (
Q0,
B,
A,
Q1,
Q2,
Q3);
output Q0;
input B;
input A;
output Q1;
output Q2;
output Q3;
// Design Ports Information
// Q0 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
// Q1 => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default
// Q2 => Location: PIN_AA2, I/O Standard: 2.5 V, Current Strength: Default
// Q3 => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default
// B => Location: PIN_W3, I/O Standard: 2.5 V, Current Strength: Default
// A => Location: PIN_W4, I/O Standard: 2.5 V, Current Strength: Default
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \~QUARTUS_CREATED_GND~I_combout ;
wire \~QUARTUS_CREATED_UNVM~~busy ;
wire \~QUARTUS_CREATED_ADC1~~eoc ;
wire \~QUARTUS_CREATED_ADC2~~eoc ;
wire \Q0~output_o ;
wire \Q1~output_o ;
wire \Q2~output_o ;
wire \Q3~output_o ;
wire \B~input_o ;
wire \A~input_o ;
wire \inst~combout ;
wire \inst2~0_combout ;
wire \inst2~1_combout ;
wire \inst2~2_combout ;
hard_block auto_generated_inst(
.devpor(devpor),
.devclrn(devclrn),
.devoe(devoe));
// Location: LCCOMB_X44_Y42_N8
fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
// Equation(s):
// \~QUARTUS_CREATED_GND~I_combout = GND
.dataa(gnd),
.datab(gnd),
.datac(gnd),
.datad(gnd),
.cin(gnd),
.combout(\~QUARTUS_CREATED_GND~I_combout ),
.cout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
// synopsys translate_on
// Location: IOOBUF_X16_Y0_N16
fiftyfivenm_io_obuf \Q0~output (
.i(!\inst~combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\Q0~output_o ),
.obar());
// synopsys translate_off
defparam \Q0~output .bus_hold = "false";
defparam \Q0~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X18_Y0_N30
fiftyfivenm_io_obuf \Q1~output (
.i(\inst2~0_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\Q1~output_o ),
.obar());
// synopsys translate_off
defparam \Q1~output .bus_hold = "false";
defparam \Q1~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X18_Y0_N23
fiftyfivenm_io_obuf \Q2~output (
.i(\inst2~1_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\Q2~output_o ),
.obar());
// synopsys translate_off
defparam \Q2~output .bus_hold = "false";
defparam \Q2~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOOBUF_X16_Y0_N2
fiftyfivenm_io_obuf \Q3~output (
.i(\inst2~2_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\Q3~output_o ),
.obar());
// synopsys translate_off
defparam \Q3~output .bus_hold = "false";
defparam \Q3~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOIBUF_X18_Y0_N8
fiftyfivenm_io_ibuf \B~input (
.i(B),
.ibar(gnd),
.nsleep(vcc),
.o(\B~input_o ));
// synopsys translate_off
defparam \B~input .bus_hold = "false";
defparam \B~input .listen_to_nsleep_signal = "false";
defparam \B~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X18_Y0_N15
fiftyfivenm_io_ibuf \A~input (
.i(A),
.ibar(gnd),
.nsleep(vcc),
.o(\A~input_o ));
// synopsys translate_off
defparam \A~input .bus_hold = "false";
defparam \A~input .listen_to_nsleep_signal = "false";
defparam \A~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LCCOMB_X18_Y1_N0
fiftyfivenm_lcell_comb inst(
// Equation(s):
// \inst~combout = (\B~input_o ) # (\A~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\B~input_o ),
.datad(\A~input_o ),
.cin(gnd),
.combout(\inst~combout ),
.cout());
// synopsys translate_off
defparam inst.lut_mask = 16'hFFF0;
defparam inst.sum_lutc_input = "datac";
// synopsys translate_on
// Location: LCCOMB_X18_Y1_N2
fiftyfivenm_lcell_comb \inst2~0 (
// Equation(s):
// \inst2~0_combout = (\B~input_o & !\A~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\B~input_o ),
.datad(\A~input_o ),
.cin(gnd),
.combout(\inst2~0_combout ),
.cout());
// synopsys translate_off
defparam \inst2~0 .lut_mask = 16'h00F0;
defparam \inst2~0 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: LCCOMB_X18_Y1_N4
fiftyfivenm_lcell_comb \inst2~1 (
// Equation(s):
// \inst2~1_combout = (!\B~input_o & \A~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\B~input_o ),
.datad(\A~input_o ),
.cin(gnd),
.combout(\inst2~1_combout ),
.cout());
// synopsys translate_off
defparam \inst2~1 .lut_mask = 16'h0F00;
defparam \inst2~1 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: LCCOMB_X18_Y1_N6
fiftyfivenm_lcell_comb \inst2~2 (
// Equation(s):
// \inst2~2_combout = (\B~input_o & \A~input_o )
.dataa(gnd),
.datab(gnd),
.datac(\B~input_o ),
.datad(\A~input_o ),
.cin(gnd),
.combout(\inst2~2_combout ),
.cout());
// synopsys translate_off
defparam \inst2~2 .lut_mask = 16'hF000;
defparam \inst2~2 .sum_lutc_input = "datac";
// synopsys translate_on
// Location: UNVM_X0_Y40_N40
fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
.arclk(vcc),
.arshft(vcc),
.drclk(vcc),
.drshft(vcc),
.drdin(vcc),
.nprogram(vcc),
.nerase(vcc),
.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
.par_en(vcc),
.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
.se(\~QUARTUS_CREATED_GND~I_combout ),
.ardin(23'b11111111111111111111111),
.busy(\~QUARTUS_CREATED_UNVM~~busy ),
.osc(),
.bgpbusy(),
.sp_pass(),
.se_pass(),
.drdout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
// synopsys translate_on
// Location: ADCBLOCK_X43_Y52_N0
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
.soc(\~QUARTUS_CREATED_GND~I_combout ),
.usr_pwd(vcc),
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
.clkin_from_pll_c0(gnd),
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
.dout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
// synopsys translate_on
// Location: ADCBLOCK_X43_Y51_N0
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
.soc(\~QUARTUS_CREATED_GND~I_combout ),
.usr_pwd(vcc),
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
.clkin_from_pll_c0(gnd),
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
.dout());
// synopsys translate_off
defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
// synopsys translate_on
assign Q0 = \Q0~output_o ;
assign Q1 = \Q1~output_o ;
assign Q2 = \Q2~output_o ;
assign Q3 = \Q3~output_o ;
endmodule
module hard_block (
devpor,
devclrn,
devoe);
// Design Ports Information
// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
input devpor;
input devclrn;
input devoe;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
wire \~ALTERA_TMS~~padout ;
wire \~ALTERA_TCK~~padout ;
wire \~ALTERA_TDI~~padout ;
wire \~ALTERA_CONFIG_SEL~~padout ;
wire \~ALTERA_nCONFIG~~padout ;
wire \~ALTERA_nSTATUS~~padout ;
wire \~ALTERA_CONF_DONE~~padout ;
wire \~ALTERA_TMS~~ibuf_o ;
wire \~ALTERA_TCK~~ibuf_o ;
wire \~ALTERA_TDI~~ibuf_o ;
wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
wire \~ALTERA_nCONFIG~~ibuf_o ;
wire \~ALTERA_nSTATUS~~ibuf_o ;
wire \~ALTERA_CONF_DONE~~ibuf_o ;
endmodule

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 200.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("A")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("B")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Q0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q3")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("A")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 40.0;
}
}
}
TRANSITION_LIST("B")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 40.0;
}
}
}
TRANSITION_LIST("Q0")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 30.0;
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 200.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("A")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("B")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Q0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
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DIRECTION = OUTPUT;
PARENT = "";
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{
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PARENT = "";
}
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WIDTH = 1;
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DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Q3")
{
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WIDTH = 1;
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EE203/Noah Woodlee/Decoder/simulation/qsim/decoder_modelsim.xrf Normal file
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vendor_name = ModelSim
source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf
source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/db/decoder.cbx.xml
design_name = decoder
instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, decoder, 1
instance = comp, \Q0~output , Q0~output, decoder, 1
instance = comp, \Q1~output , Q1~output, decoder, 1
instance = comp, \Q2~output , Q2~output, decoder, 1
instance = comp, \Q3~output , Q3~output, decoder, 1
instance = comp, \B~input , B~input, decoder, 1
instance = comp, \A~input , A~input, decoder, 1
instance = comp, \inst2~0 , inst2~0, decoder, 1
instance = comp, \inst2~1 , inst2~1, decoder, 1
instance = comp, \inst2~2 , inst2~2, decoder, 1
instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, decoder, 1
instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, decoder, 1
instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, decoder, 1
design_name = hard_block
instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1
instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1
instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1
instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1
instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1
instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1
instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1

37
EE203/Noah Woodlee/Decoder/simulation/qsim/transcript Normal file
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# do decoder.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:12:11 on Jan 21,2021
# vlog -work work decoder.vo
# -- Compiling module decoder
# -- Compiling module hard_block
#
# Top level modules:
# decoder
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:12:12 on Jan 21,2021
# vlog -work work Waveform.vwf.vt
# -- Compiling module decoder_vlg_vec_tst
#
# Top level modules:
# decoder_vlg_vec_tst
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst
# Start time: 20:12:12 on Jan 21,2021
# Loading work.decoder_vlg_vec_tst
# Loading work.decoder
# Loading work.hard_block
# ** Warning: (vsim-3017) decoder.vo(284): [TFMPC] - Too few port connections. Expected 8, found 7.
# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile
# ** Warning: (vsim-3722) decoder.vo(284): [TFMPC] - Missing connection for port 'clk_dft'.
# ** Warning: (vsim-3017) decoder.vo(307): [TFMPC] - Too few port connections. Expected 8, found 7.
# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile
# ** Warning: (vsim-3722) decoder.vo(307): [TFMPC] - Missing connection for port 'clk_dft'.
# after#26
# ** Note: $finish : Waveform.vwf.vt(53)
# Time: 200 ns Iteration: 0 Instance: /decoder_vlg_vec_tst
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 4

141
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Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Intel and sold by Intel or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Thu Jan 21 20:12:10 2021
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder -c decoder --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/Waveform.vwf.vt"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Intel and sold by Intel or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Thu Jan 21 20:12:11 2021
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/" decoder -c decoder
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file decoder.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4641 megabytes
Info: Processing ended: Thu Jan 21 20:12:11 2021
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
Completed successfully.
**** Generating the ModelSim .do script ****
C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do decoder.do
Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl
# 10.5b
# do decoder.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:12:11 on Jan 21,2021
# vlog -work work decoder.vo
# -- Compiling module decoder
# -- Compiling module hard_block
#
# Top level modules:
# decoder
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:12:12 on Jan 21,2021
# vlog -work work Waveform.vwf.vt
# -- Compiling module decoder_vlg_vec_tst
#
# Top level modules:
# decoder_vlg_vec_tst
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.decoder_vlg_vec_tst
# Start time: 20:12:12 on Jan 21,2021
# Loading work.decoder_vlg_vec_tst
# Loading work.decoder
# Loading work.hard_block
# ** Warning: (vsim-3017) decoder.vo(284): [TFMPC] - Too few port connections. Expected 8, found 7.
# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile
# ** Warning: (vsim-3722) decoder.vo(284): [TFMPC] - Missing connection for port 'clk_dft'.
# ** Warning: (vsim-3017) decoder.vo(307): [TFMPC] - Too few port connections. Expected 8, found 7.
# Time: 0 ps Iteration: 0 Instance: /decoder_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile
# ** Warning: (vsim-3722) decoder.vo(307): [TFMPC] - Missing connection for port 'clk_dft'.
# after#26
# ** Note: $finish : Waveform.vwf.vt(53)
# Time: 200 ns Iteration: 0 Instance: /decoder_vlg_vec_tst
# End time: 20:12:12 on Jan 21,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 4
Completed successfully.
**** Converting ModelSim VCD to vector waveform ****
Reading C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/Waveform.vwf...
Reading C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder.msim.vcd...
Processing channel transitions...
Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/decoder_20210121201212.sim.vwf
Finished VCD to VWF conversion.
Completed successfully.
All completed.

73
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