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Andrew W
2022-08-28 16:12:16 -05:00
parent 5a2894ed1b
commit 7dabaef6f6
2345 changed files with 1343530 additions and 0 deletions
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614299275561 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614299275571 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 18:27:55 2021 " "Processing started: Thu Feb 25 18:27:55 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614299275571 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1614299275571 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1614299275571 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1614299275861 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1614299277691 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1614299277841 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614299278941 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 18:27:58 2021 " "Processing ended: Thu Feb 25 18:27:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614299278941 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614299278941 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614299278941 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1614299278941 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="decoder">
</PROJECT>
</LOG_ROOT>

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EE203/Noah Woodlee/LAB1/Decoder/db/decoder.cmp.logdb Normal file
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v1
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,6;0;6;0;0;6;6;0;6;6;0;4;0;0;2;0;4;2;0;0;0;4;0;0;0;0;0;6;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,0;6;0;6;6;0;0;6;0;0;6;2;6;6;4;6;2;4;6;6;6;2;6;6;6;6;6;0;6;6,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Q0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Q1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Q2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Q3,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,B,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,A,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,

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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Thu Apr 22 15:44:18 2021

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1611281531256 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2016 Intel Corporation. All rights reserved. " "Copyright (C) 2016 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic " "and other software and tools, and its AMPP partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel MegaCore Function License Agreement, or other " "the Intel MegaCore Function License Agreement, or other " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable license agreement, including, without limitation, " "applicable license agreement, including, without limitation, " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "that your use is for the sole purpose of programming logic " "that your use is for the sole purpose of programming logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "devices manufactured by Intel and sold by Intel or its " "devices manufactured by Intel and sold by Intel or its " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "authorized distributors. Please refer to the applicable " "authorized distributors. Please refer to the applicable " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement for further details. " "agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 20:12:11 2021 " "Processing started: Thu Jan 21 20:12:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1611281531260 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531260 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/\" decoder -c decoder " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=\"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim/\" decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531261 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1611281531461 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder.vo C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim// simulation " "Generated file decoder.vo in folder \"C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1611281531492 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4641 " "Peak virtual memory: 4641 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 20:12:11 2021 " "Processing ended: Thu Jan 21 20:12:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1611281531521 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1611281531521 ""}

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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1614299267691 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1614299267691 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "decoder 10M50DAF484C7G " "Selected device 10M50DAF484C7G for design \"decoder\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1614299267701 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1614299267731 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1614299267731 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1614299268071 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1614299268101 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF484I7G " "Device 10M08DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484C7G " "Device 10M16DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF484I7G " "Device 10M16DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484C7G " "Device 10M25DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF484I7G " "Device 10M25DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7G " "Device 10M50DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF484I7P " "Device 10M50DAF484I7P is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484C7G " "Device 10M40DAF484C7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF484I7G " "Device 10M40DAF484I7G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1614299268301 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1614299268301 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ H2 " "Pin ~ALTERA_TMS~ is reserved at location H2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 26 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ G2 " "Pin ~ALTERA_TCK~ is reserved at location G2" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 28 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ L4 " "Pin ~ALTERA_TDI~ is reserved at location L4" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 30 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ M5 " "Pin ~ALTERA_TDO~ is reserved at location M5" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 32 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ H10 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 34 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ H9 " "Pin ~ALTERA_nCONFIG~ is reserved at location H9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 36 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ G9 " "Pin ~ALTERA_nSTATUS~ is reserved at location G9" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 38 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ F8 " "Pin ~ALTERA_CONF_DONE~ is reserved at location F8" { } { { "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/16.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 0 { 0 ""} 0 40 14176 15139 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1614299268321 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1614299268321 ""}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614299268321 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614299268321 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614299268321 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1614299268321 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1614299268331 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "decoder.sdc " "Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1614299268901 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1614299268901 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1614299268901 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1614299268911 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1614299268911 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1614299268911 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1614299268911 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1614299268911 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1614299268911 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1614299268911 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1614299268911 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1614299268911 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1614299268911 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1614299268911 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1614299268911 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1614299268911 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1614299268911 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1614299268911 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614299268931 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1614299268951 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1614299270111 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614299270181 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1614299270221 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1614299270401 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614299270401 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1614299270841 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X45_Y44 X55_Y54 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54" { } { { "loc" "" { Generic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X45_Y44 to location X55_Y54"} { { 12 { 0 ""} 45 44 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1614299272191 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1614299272191 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1614299272301 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1614299272301 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1614299272301 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614299272311 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1614299272521 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1614299272531 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1614299272771 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1614299272771 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1614299273101 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1614299273551 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg " "Generated suppressed messages file C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/output_files/decoder.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1614299273841 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5904 " "Peak virtual memory: 5904 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614299274401 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 18:27:54 2021 " "Processing ended: Thu Feb 25 18:27:54 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614299274401 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614299274401 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614299274401 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1614299274401 ""}

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EE203/Noah Woodlee/LAB1/Decoder/db/decoder.hier_info Normal file
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|decoder
Q0 <= inst.DB_MAX_OUTPUT_PORT_TYPE
B => inst7.IN0
B => inst1.IN1
B => inst3.IN1
A => inst5.IN0
A => inst2.IN0
A => inst3.IN0
Q1 <= inst1.DB_MAX_OUTPUT_PORT_TYPE
Q2 <= inst2.DB_MAX_OUTPUT_PORT_TYPE
Q3 <= inst3.DB_MAX_OUTPUT_PORT_TYPE

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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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v1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614299254641 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614299254641 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 18:27:34 2021 " "Processing started: Thu Feb 25 18:27:34 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614299254641 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614299254641 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder " "Command: quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614299254641 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1614299255111 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1614299255111 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file decoder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Found entity 1: decoder" { } { { "decoder.bdf" "" { Schematic "C:/Users/anw0044/Desktop/Noah Woodlee/Decoder/decoder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1614299263471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1614299263471 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "decoder " "Elaborating entity \"decoder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1614299263531 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1614299264081 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1614299264661 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1614299264661 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1614299264841 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1614299264841 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1614299264841 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1614299264841 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4781 " "Peak virtual memory: 4781 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614299264881 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 18:27:44 2021 " "Processing ended: Thu Feb 25 18:27:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614299264881 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614299264881 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614299264881 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1614299264881 ""}

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v1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1614299280231 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1614299280241 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 25 18:27:59 2021 " "Processing started: Thu Feb 25 18:27:59 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1614299280241 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280241 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta decoder -c decoder " "Command: quartus_sta decoder -c decoder" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280241 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280371 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280531 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280531 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280561 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280561 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "decoder.sdc " "Synopsys Design Constraints File file not found: 'decoder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280851 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280861 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280871 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280881 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280881 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280881 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280891 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280901 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280911 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280911 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280921 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299280931 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299280961 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281341 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281411 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281411 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281411 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281411 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281421 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281431 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281441 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281441 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281451 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281461 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1614299281461 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281651 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281661 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281661 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281671 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299281681 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299282471 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299282471 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1614299282531 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 25 18:28:02 2021 " "Processing ended: Thu Feb 25 18:28:02 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1614299282531 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1614299282531 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1614299282531 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1614299282531 ""}

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start_full_compilation:s
start_assembler:s-start_full_compilation
start_timing_analyzer:s-start_full_compilation

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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "Q0",
"strict" : false
},
{
"name" : "Q1",
"strict" : false
},
{
"name" : "Q2",
"strict" : false
},
{
"name" : "Q3",
"strict" : false
},
{
"name" : "B",
"strict" : false
},
{
"name" : "A",
"strict" : false
}
]
}
]
}