added more code
This commit is contained in:
Andrew W
17
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.do
Normal file
17
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.do
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@@ -0,0 +1,17 @@
|
||||
onerror {exit -code 1}
|
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vlib work
|
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vlog -work work Lab1Pt1.vo
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vlog -work work Waveform.vwf.vt
|
||||
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst
|
||||
vcd file -direction Lab1Pt1.msim.vcd
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||||
vcd add -internal Lab1Pt1_vlg_vec_tst/*
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vcd add -internal Lab1Pt1_vlg_vec_tst/i1/*
|
||||
proc simTimestamp {} {
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echo "Simulation time: $::now ps"
|
||||
if { [string equal running [runStatus]] } {
|
||||
after 2500 simTimestamp
|
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}
|
||||
}
|
||||
after 2500 simTimestamp
|
||||
run -all
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quit -f
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@@ -0,0 +1,300 @@
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$comment
|
||||
File created using the following command:
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vcd file Lab1Pt1.msim.vcd -direction
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$end
|
||||
$date
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Thu Feb 25 20:02:14 2021
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||||
$end
|
||||
$version
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||||
ModelSim Version 10.5b
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||||
$end
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$timescale
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1ps
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$end
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||||
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$scope module Lab1Pt1_vlg_vec_tst $end
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$var reg 10 ! SW [9:0] $end
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||||
$var wire 1 " LEDR [9] $end
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||||
$var wire 1 # LEDR [8] $end
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$var wire 1 $ LEDR [7] $end
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||||
$var wire 1 % LEDR [6] $end
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||||
$var wire 1 & LEDR [5] $end
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||||
$var wire 1 ' LEDR [4] $end
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||||
$var wire 1 ( LEDR [3] $end
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||||
$var wire 1 ) LEDR [2] $end
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||||
$var wire 1 * LEDR [1] $end
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$var wire 1 + LEDR [0] $end
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||||
|
||||
$scope module i1 $end
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||||
$var wire 1 , gnd $end
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||||
$var wire 1 - vcc $end
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||||
$var wire 1 . unknown $end
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||||
$var tri1 1 / devclrn $end
|
||||
$var tri1 1 0 devpor $end
|
||||
$var tri1 1 1 devoe $end
|
||||
$var wire 1 2 ~QUARTUS_CREATED_GND~I_combout $end
|
||||
$var wire 1 3 ~QUARTUS_CREATED_UNVM~~busy $end
|
||||
$var wire 1 4 ~QUARTUS_CREATED_ADC1~~eoc $end
|
||||
$var wire 1 5 ~QUARTUS_CREATED_ADC2~~eoc $end
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||||
$var wire 1 6 LEDR[0]~output_o $end
|
||||
$var wire 1 7 LEDR[1]~output_o $end
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||||
$var wire 1 8 LEDR[2]~output_o $end
|
||||
$var wire 1 9 LEDR[3]~output_o $end
|
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$var wire 1 : LEDR[4]~output_o $end
|
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$var wire 1 ; LEDR[5]~output_o $end
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$var wire 1 < LEDR[6]~output_o $end
|
||||
$var wire 1 = LEDR[7]~output_o $end
|
||||
$var wire 1 > LEDR[8]~output_o $end
|
||||
$var wire 1 ? LEDR[9]~output_o $end
|
||||
$var wire 1 @ SW[0]~input_o $end
|
||||
$var wire 1 A SW[1]~input_o $end
|
||||
$var wire 1 B SW[2]~input_o $end
|
||||
$var wire 1 C SW[3]~input_o $end
|
||||
$var wire 1 D SW[4]~input_o $end
|
||||
$var wire 1 E SW[5]~input_o $end
|
||||
$var wire 1 F SW[6]~input_o $end
|
||||
$var wire 1 G SW[7]~input_o $end
|
||||
$var wire 1 H SW[8]~input_o $end
|
||||
$var wire 1 I SW[9]~input_o $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b0 !
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0+
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0*
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0)
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0(
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0'
|
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0&
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0%
|
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0$
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0#
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0"
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0,
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1-
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x.
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1/
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10
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11
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02
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z3
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z4
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z5
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06
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07
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08
|
||||
09
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||||
0:
|
||||
0;
|
||||
0<
|
||||
0=
|
||||
0>
|
||||
0?
|
||||
0@
|
||||
0A
|
||||
0B
|
||||
0C
|
||||
0D
|
||||
0E
|
||||
0F
|
||||
0G
|
||||
0H
|
||||
0I
|
||||
$end
|
||||
#10000
|
||||
b1000000000 !
|
||||
1I
|
||||
1?
|
||||
1"
|
||||
#20000
|
||||
b0 !
|
||||
0I
|
||||
0?
|
||||
0"
|
||||
#30000
|
||||
b100000000 !
|
||||
b110000000 !
|
||||
b111000000 !
|
||||
b111100000 !
|
||||
b111110000 !
|
||||
b111111000 !
|
||||
b111111100 !
|
||||
b111111110 !
|
||||
b111111111 !
|
||||
b1111111111 !
|
||||
1I
|
||||
1H
|
||||
1G
|
||||
1F
|
||||
1E
|
||||
1D
|
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1C
|
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1B
|
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1A
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1@
|
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16
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17
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18
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19
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1:
|
||||
1;
|
||||
1<
|
||||
1=
|
||||
1>
|
||||
1?
|
||||
1"
|
||||
1#
|
||||
1$
|
||||
1%
|
||||
1&
|
||||
1'
|
||||
1(
|
||||
1)
|
||||
1*
|
||||
1+
|
||||
#40000
|
||||
b1011111111 !
|
||||
b1001111111 !
|
||||
b1000111111 !
|
||||
b1000011111 !
|
||||
b1000001111 !
|
||||
b1000000111 !
|
||||
b1000000011 !
|
||||
b1000000001 !
|
||||
b1000000000 !
|
||||
b0 !
|
||||
0I
|
||||
0H
|
||||
0G
|
||||
0F
|
||||
0E
|
||||
0D
|
||||
0C
|
||||
0B
|
||||
0A
|
||||
0@
|
||||
06
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||||
07
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||||
08
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||||
09
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||||
0:
|
||||
0;
|
||||
0<
|
||||
0=
|
||||
0>
|
||||
0?
|
||||
0"
|
||||
0#
|
||||
0$
|
||||
0%
|
||||
0&
|
||||
0'
|
||||
0(
|
||||
0)
|
||||
0*
|
||||
0+
|
||||
#60000
|
||||
b100000 !
|
||||
1E
|
||||
1;
|
||||
1&
|
||||
#130000
|
||||
b0 !
|
||||
0E
|
||||
0;
|
||||
0&
|
||||
#200000
|
||||
b1000000000 !
|
||||
1I
|
||||
1?
|
||||
1"
|
||||
#260000
|
||||
b1100000000 !
|
||||
b100000000 !
|
||||
0I
|
||||
1H
|
||||
1>
|
||||
0?
|
||||
0"
|
||||
1#
|
||||
#300000
|
||||
b110000000 !
|
||||
b10000000 !
|
||||
0H
|
||||
1G
|
||||
1=
|
||||
0>
|
||||
0#
|
||||
1$
|
||||
#340000
|
||||
b0 !
|
||||
0G
|
||||
0=
|
||||
0$
|
||||
#350000
|
||||
b1000000 !
|
||||
1F
|
||||
1<
|
||||
1%
|
||||
#370000
|
||||
b1100000 !
|
||||
b100000 !
|
||||
0F
|
||||
1E
|
||||
1;
|
||||
0<
|
||||
0%
|
||||
1&
|
||||
#390000
|
||||
b110000 !
|
||||
b10000 !
|
||||
0E
|
||||
1D
|
||||
1:
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||||
0;
|
||||
0&
|
||||
1'
|
||||
#410000
|
||||
b11000 !
|
||||
b1000 !
|
||||
0D
|
||||
1C
|
||||
19
|
||||
0:
|
||||
0'
|
||||
1(
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||||
#430000
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||||
b1100 !
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||||
b100 !
|
||||
0C
|
||||
1B
|
||||
18
|
||||
09
|
||||
0(
|
||||
1)
|
||||
#450000
|
||||
b110 !
|
||||
b10 !
|
||||
0B
|
||||
1A
|
||||
17
|
||||
08
|
||||
0)
|
||||
1*
|
||||
#470000
|
||||
b11 !
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||||
b1 !
|
||||
0A
|
||||
1@
|
||||
16
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||||
07
|
||||
0*
|
||||
1+
|
||||
#490000
|
||||
b0 !
|
||||
0@
|
||||
06
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||||
0+
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||||
#1000000
|
||||
@@ -0,0 +1 @@
|
||||
set tool_name "ModelSim-Altera (Verilog)"
|
||||
517
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.vo
Normal file
517
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.vo
Normal file
@@ -0,0 +1,517 @@
|
||||
// Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel MegaCore Function License Agreement, or other
|
||||
// applicable license agreement, including, without limitation,
|
||||
// that your use is for the sole purpose of programming logic
|
||||
// devices manufactured by Intel and sold by Intel or its
|
||||
// authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
// VENDOR "Altera"
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition"
|
||||
|
||||
// DATE "02/25/2021 20:02:11"
|
||||
|
||||
//
|
||||
// Device: Altera 10M50DAF484C7G Package FBGA484
|
||||
//
|
||||
|
||||
//
|
||||
// This Verilog file should be used for ModelSim-Altera (Verilog) only
|
||||
//
|
||||
|
||||
`timescale 1 ps/ 1 ps
|
||||
|
||||
module Lab1Pt1 (
|
||||
SW,
|
||||
LEDR);
|
||||
input [9:0] SW;
|
||||
output [9:0] LEDR;
|
||||
|
||||
// Design Ports Information
|
||||
// LEDR[0] => Location: PIN_J8, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[1] => Location: PIN_J20, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[2] => Location: PIN_L9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[3] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[4] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[5] => Location: PIN_M18, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[6] => Location: PIN_T5, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[7] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[8] => Location: PIN_W15, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[9] => Location: PIN_AB9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[0] => Location: PIN_J9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[1] => Location: PIN_H20, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[2] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[3] => Location: PIN_R22, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[4] => Location: PIN_W14, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[5] => Location: PIN_L19, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[6] => Location: PIN_R1, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[7] => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[8] => Location: PIN_Y16, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[9] => Location: PIN_AA9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
|
||||
|
||||
wire gnd;
|
||||
wire vcc;
|
||||
wire unknown;
|
||||
|
||||
assign gnd = 1'b0;
|
||||
assign vcc = 1'b1;
|
||||
assign unknown = 1'bx;
|
||||
|
||||
tri1 devclrn;
|
||||
tri1 devpor;
|
||||
tri1 devoe;
|
||||
wire \~QUARTUS_CREATED_GND~I_combout ;
|
||||
wire \~QUARTUS_CREATED_UNVM~~busy ;
|
||||
wire \~QUARTUS_CREATED_ADC1~~eoc ;
|
||||
wire \~QUARTUS_CREATED_ADC2~~eoc ;
|
||||
wire \LEDR[0]~output_o ;
|
||||
wire \LEDR[1]~output_o ;
|
||||
wire \LEDR[2]~output_o ;
|
||||
wire \LEDR[3]~output_o ;
|
||||
wire \LEDR[4]~output_o ;
|
||||
wire \LEDR[5]~output_o ;
|
||||
wire \LEDR[6]~output_o ;
|
||||
wire \LEDR[7]~output_o ;
|
||||
wire \LEDR[8]~output_o ;
|
||||
wire \LEDR[9]~output_o ;
|
||||
wire \SW[0]~input_o ;
|
||||
wire \SW[1]~input_o ;
|
||||
wire \SW[2]~input_o ;
|
||||
wire \SW[3]~input_o ;
|
||||
wire \SW[4]~input_o ;
|
||||
wire \SW[5]~input_o ;
|
||||
wire \SW[6]~input_o ;
|
||||
wire \SW[7]~input_o ;
|
||||
wire \SW[8]~input_o ;
|
||||
wire \SW[9]~input_o ;
|
||||
|
||||
|
||||
hard_block auto_generated_inst(
|
||||
.devpor(devpor),
|
||||
.devclrn(devclrn),
|
||||
.devoe(devoe));
|
||||
|
||||
// Location: LCCOMB_X44_Y51_N16
|
||||
fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
|
||||
// Equation(s):
|
||||
// \~QUARTUS_CREATED_GND~I_combout = GND
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(gnd),
|
||||
.datac(gnd),
|
||||
.datad(gnd),
|
||||
.cin(gnd),
|
||||
.combout(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
|
||||
defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X0_Y36_N16
|
||||
fiftyfivenm_io_obuf \LEDR[0]~output (
|
||||
.i(\SW[0]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[0]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[0]~output .bus_hold = "false";
|
||||
defparam \LEDR[0]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X78_Y45_N9
|
||||
fiftyfivenm_io_obuf \LEDR[1]~output (
|
||||
.i(\SW[1]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[1]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[1]~output .bus_hold = "false";
|
||||
defparam \LEDR[1]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X0_Y27_N23
|
||||
fiftyfivenm_io_obuf \LEDR[2]~output (
|
||||
.i(\SW[2]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[2]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[2]~output .bus_hold = "false";
|
||||
defparam \LEDR[2]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X78_Y21_N16
|
||||
fiftyfivenm_io_obuf \LEDR[3]~output (
|
||||
.i(\SW[3]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[3]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[3]~output .bus_hold = "false";
|
||||
defparam \LEDR[3]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X49_Y0_N2
|
||||
fiftyfivenm_io_obuf \LEDR[4]~output (
|
||||
.i(\SW[4]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[4]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[4]~output .bus_hold = "false";
|
||||
defparam \LEDR[4]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X78_Y37_N23
|
||||
fiftyfivenm_io_obuf \LEDR[5]~output (
|
||||
.i(\SW[5]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[5]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[5]~output .bus_hold = "false";
|
||||
defparam \LEDR[5]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X0_Y3_N16
|
||||
fiftyfivenm_io_obuf \LEDR[6]~output (
|
||||
.i(\SW[6]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[6]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[6]~output .bus_hold = "false";
|
||||
defparam \LEDR[6]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X22_Y39_N30
|
||||
fiftyfivenm_io_obuf \LEDR[7]~output (
|
||||
.i(\SW[7]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[7]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[7]~output .bus_hold = "false";
|
||||
defparam \LEDR[7]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X54_Y0_N9
|
||||
fiftyfivenm_io_obuf \LEDR[8]~output (
|
||||
.i(\SW[8]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[8]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[8]~output .bus_hold = "false";
|
||||
defparam \LEDR[8]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X34_Y0_N16
|
||||
fiftyfivenm_io_obuf \LEDR[9]~output (
|
||||
.i(\SW[9]~input_o ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[9]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[9]~output .bus_hold = "false";
|
||||
defparam \LEDR[9]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X0_Y36_N22
|
||||
fiftyfivenm_io_ibuf \SW[0]~input (
|
||||
.i(SW[0]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[0]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[0]~input .bus_hold = "false";
|
||||
defparam \SW[0]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[0]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X78_Y45_N1
|
||||
fiftyfivenm_io_ibuf \SW[1]~input (
|
||||
.i(SW[1]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[1]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[1]~input .bus_hold = "false";
|
||||
defparam \SW[1]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[1]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X0_Y27_N1
|
||||
fiftyfivenm_io_ibuf \SW[2]~input (
|
||||
.i(SW[2]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[2]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[2]~input .bus_hold = "false";
|
||||
defparam \SW[2]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[2]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X78_Y21_N8
|
||||
fiftyfivenm_io_ibuf \SW[3]~input (
|
||||
.i(SW[3]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[3]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[3]~input .bus_hold = "false";
|
||||
defparam \SW[3]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[3]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X49_Y0_N22
|
||||
fiftyfivenm_io_ibuf \SW[4]~input (
|
||||
.i(SW[4]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[4]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[4]~input .bus_hold = "false";
|
||||
defparam \SW[4]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[4]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X78_Y37_N8
|
||||
fiftyfivenm_io_ibuf \SW[5]~input (
|
||||
.i(SW[5]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[5]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[5]~input .bus_hold = "false";
|
||||
defparam \SW[5]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[5]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X0_Y3_N1
|
||||
fiftyfivenm_io_ibuf \SW[6]~input (
|
||||
.i(SW[6]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[6]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[6]~input .bus_hold = "false";
|
||||
defparam \SW[6]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[6]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X22_Y39_N15
|
||||
fiftyfivenm_io_ibuf \SW[7]~input (
|
||||
.i(SW[7]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[7]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[7]~input .bus_hold = "false";
|
||||
defparam \SW[7]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[7]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X54_Y0_N22
|
||||
fiftyfivenm_io_ibuf \SW[8]~input (
|
||||
.i(SW[8]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[8]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[8]~input .bus_hold = "false";
|
||||
defparam \SW[8]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[8]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X34_Y0_N22
|
||||
fiftyfivenm_io_ibuf \SW[9]~input (
|
||||
.i(SW[9]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[9]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[9]~input .bus_hold = "false";
|
||||
defparam \SW[9]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[9]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: UNVM_X0_Y40_N40
|
||||
fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
|
||||
.arclk(vcc),
|
||||
.arshft(vcc),
|
||||
.drclk(vcc),
|
||||
.drshft(vcc),
|
||||
.drdin(vcc),
|
||||
.nprogram(vcc),
|
||||
.nerase(vcc),
|
||||
.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.par_en(vcc),
|
||||
.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.se(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.ardin(23'b11111111111111111111111),
|
||||
.busy(\~QUARTUS_CREATED_UNVM~~busy ),
|
||||
.osc(),
|
||||
.bgpbusy(),
|
||||
.sp_pass(),
|
||||
.se_pass(),
|
||||
.drdout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: ADCBLOCK_X43_Y52_N0
|
||||
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
|
||||
.soc(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.usr_pwd(vcc),
|
||||
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.clkin_from_pll_c0(gnd),
|
||||
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
|
||||
.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
|
||||
.dout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: ADCBLOCK_X43_Y51_N0
|
||||
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
|
||||
.soc(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.usr_pwd(vcc),
|
||||
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.clkin_from_pll_c0(gnd),
|
||||
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
|
||||
.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
|
||||
.dout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
|
||||
// synopsys translate_on
|
||||
|
||||
assign LEDR[0] = \LEDR[0]~output_o ;
|
||||
|
||||
assign LEDR[1] = \LEDR[1]~output_o ;
|
||||
|
||||
assign LEDR[2] = \LEDR[2]~output_o ;
|
||||
|
||||
assign LEDR[3] = \LEDR[3]~output_o ;
|
||||
|
||||
assign LEDR[4] = \LEDR[4]~output_o ;
|
||||
|
||||
assign LEDR[5] = \LEDR[5]~output_o ;
|
||||
|
||||
assign LEDR[6] = \LEDR[6]~output_o ;
|
||||
|
||||
assign LEDR[7] = \LEDR[7]~output_o ;
|
||||
|
||||
assign LEDR[8] = \LEDR[8]~output_o ;
|
||||
|
||||
assign LEDR[9] = \LEDR[9]~output_o ;
|
||||
|
||||
endmodule
|
||||
|
||||
module hard_block (
|
||||
|
||||
devpor,
|
||||
devclrn,
|
||||
devoe);
|
||||
|
||||
// Design Ports Information
|
||||
// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
|
||||
input devpor;
|
||||
input devclrn;
|
||||
input devoe;
|
||||
|
||||
wire gnd;
|
||||
wire vcc;
|
||||
wire unknown;
|
||||
|
||||
assign gnd = 1'b0;
|
||||
assign vcc = 1'b1;
|
||||
assign unknown = 1'bx;
|
||||
|
||||
wire \~ALTERA_TMS~~padout ;
|
||||
wire \~ALTERA_TCK~~padout ;
|
||||
wire \~ALTERA_TDI~~padout ;
|
||||
wire \~ALTERA_CONFIG_SEL~~padout ;
|
||||
wire \~ALTERA_nCONFIG~~padout ;
|
||||
wire \~ALTERA_nSTATUS~~padout ;
|
||||
wire \~ALTERA_CONF_DONE~~padout ;
|
||||
wire \~ALTERA_TMS~~ibuf_o ;
|
||||
wire \~ALTERA_TCK~~ibuf_o ;
|
||||
wire \~ALTERA_TDI~~ibuf_o ;
|
||||
wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
|
||||
wire \~ALTERA_nCONFIG~~ibuf_o ;
|
||||
wire \~ALTERA_nSTATUS~~ibuf_o ;
|
||||
wire \~ALTERA_CONF_DONE~~ibuf_o ;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,829 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel MegaCore Function License Agreement, or other
|
||||
applicable license agreement, including, without limitation,
|
||||
that your use is for the sole purpose of programming logic
|
||||
devices manufactured by Intel and sold by Intel or its
|
||||
authorized distributors. Please refer to the applicable
|
||||
agreement for further details.
|
||||
*/
|
||||
|
||||
HEADER
|
||||
{
|
||||
VERSION = 1;
|
||||
TIME_UNIT = ns;
|
||||
DATA_OFFSET = 0.0;
|
||||
DATA_DURATION = 1000.0;
|
||||
SIMULATION_TIME = 0.0;
|
||||
GRID_PHASE = 0.0;
|
||||
GRID_PERIOD = 10.0;
|
||||
GRID_DUTY_CYCLE = 50;
|
||||
}
|
||||
|
||||
SIGNAL("LEDR")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = BUS;
|
||||
WIDTH = 10;
|
||||
LSB_INDEX = 0;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[9]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[8]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[7]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[6]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[5]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[4]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[3]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[2]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[1]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[0]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("SW")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = BUS;
|
||||
WIDTH = 10;
|
||||
LSB_INDEX = 0;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("SW[9]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[8]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[7]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[6]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[5]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[4]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[3]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[2]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[1]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[0]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[9]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 10.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 10.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 160.0;
|
||||
LEVEL 1 FOR 60.0;
|
||||
LEVEL 0 FOR 740.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[8]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 220.0;
|
||||
LEVEL 1 FOR 40.0;
|
||||
LEVEL 0 FOR 700.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[7]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 260.0;
|
||||
LEVEL 1 FOR 40.0;
|
||||
LEVEL 0 FOR 660.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[6]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 310.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 630.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[5]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 20.0;
|
||||
LEVEL 1 FOR 70.0;
|
||||
LEVEL 0 FOR 240.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 610.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 350.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 590.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 370.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 570.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 390.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 550.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 410.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 530.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 430.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 510.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[9]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 10.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 10.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 160.0;
|
||||
LEVEL 1 FOR 60.0;
|
||||
LEVEL 0 FOR 740.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[8]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 220.0;
|
||||
LEVEL 1 FOR 40.0;
|
||||
LEVEL 0 FOR 700.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[7]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 260.0;
|
||||
LEVEL 1 FOR 40.0;
|
||||
LEVEL 0 FOR 660.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[6]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 310.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 630.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[5]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 20.0;
|
||||
LEVEL 1 FOR 70.0;
|
||||
LEVEL 0 FOR 240.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 610.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 350.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 590.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 370.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 570.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 390.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 550.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 410.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 530.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
LEVEL 0 FOR 430.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
LEVEL 0 FOR 510.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR";
|
||||
EXPAND_STATUS = EXPANDED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 0;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[9]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 1;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[8]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 2;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[7]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 3;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[6]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 4;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[5]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 5;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 6;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 7;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 8;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 9;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 10;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW";
|
||||
EXPAND_STATUS = EXPANDED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 11;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19, 20, 21;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[9]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 12;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[8]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 13;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[7]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 14;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[6]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 15;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[5]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 16;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 17;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 18;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 19;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 20;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 21;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 11;
|
||||
}
|
||||
|
||||
TIME_BAR
|
||||
{
|
||||
TIME = 0;
|
||||
MASTER = TRUE;
|
||||
}
|
||||
;
|
||||
@@ -0,0 +1,36 @@
|
||||
vendor_name = ModelSim
|
||||
source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Lab1Pt1.v
|
||||
source_file = 1, C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/db/Lab1Pt1.cbx.xml
|
||||
design_name = Lab1Pt1
|
||||
instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[0]~output , LEDR[0]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[1]~output , LEDR[1]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[2]~output , LEDR[2]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[3]~output , LEDR[3]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[4]~output , LEDR[4]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[5]~output , LEDR[5]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[6]~output , LEDR[6]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[7]~output , LEDR[7]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[8]~output , LEDR[8]~output, Lab1Pt1, 1
|
||||
instance = comp, \LEDR[9]~output , LEDR[9]~output, Lab1Pt1, 1
|
||||
instance = comp, \SW[0]~input , SW[0]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[1]~input , SW[1]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[2]~input , SW[2]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[3]~input , SW[3]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[4]~input , SW[4]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[5]~input , SW[5]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[6]~input , SW[6]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[7]~input , SW[7]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[8]~input , SW[8]~input, Lab1Pt1, 1
|
||||
instance = comp, \SW[9]~input , SW[9]~input, Lab1Pt1, 1
|
||||
instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, Lab1Pt1, 1
|
||||
instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, Lab1Pt1, 1
|
||||
instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, Lab1Pt1, 1
|
||||
design_name = hard_block
|
||||
instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1
|
||||
@@ -0,0 +1,142 @@
|
||||
// Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel MegaCore Function License Agreement, or other
|
||||
// applicable license agreement, including, without limitation,
|
||||
// that your use is for the sole purpose of programming logic
|
||||
// devices manufactured by Intel and sold by Intel or its
|
||||
// authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
// *****************************************************************************
|
||||
// This file contains a Verilog test bench with test vectors .The test vectors
|
||||
// are exported from a vector file in the Quartus Waveform Editor and apply to
|
||||
// the top level entity of the current Quartus project .The user can use this
|
||||
// testbench to simulate his design using a third-party simulation tool .
|
||||
// *****************************************************************************
|
||||
// Generated on "02/25/2021 20:02:10"
|
||||
|
||||
// Verilog Test Bench (with test vectors) for design : Lab1Pt1
|
||||
//
|
||||
// Simulation tool : 3rd Party
|
||||
//
|
||||
|
||||
`timescale 1 ps/ 1 ps
|
||||
module Lab1Pt1_vlg_vec_tst();
|
||||
// constants
|
||||
// general purpose registers
|
||||
reg [9:0] SW;
|
||||
// wires
|
||||
wire [9:0] LEDR;
|
||||
|
||||
// assign statements (if any)
|
||||
Lab1Pt1 i1 (
|
||||
// port map - connection between master ports and signals/registers
|
||||
.LEDR(LEDR),
|
||||
.SW(SW)
|
||||
);
|
||||
initial
|
||||
begin
|
||||
#1000000 $finish;
|
||||
end
|
||||
// SW[ 9 ]
|
||||
initial
|
||||
begin
|
||||
SW[9] = 1'b0;
|
||||
SW[9] = #10000 1'b1;
|
||||
SW[9] = #10000 1'b0;
|
||||
SW[9] = #10000 1'b1;
|
||||
SW[9] = #10000 1'b0;
|
||||
SW[9] = #160000 1'b1;
|
||||
SW[9] = #60000 1'b0;
|
||||
end
|
||||
// SW[ 8 ]
|
||||
initial
|
||||
begin
|
||||
SW[8] = 1'b0;
|
||||
SW[8] = #30000 1'b1;
|
||||
SW[8] = #10000 1'b0;
|
||||
SW[8] = #220000 1'b1;
|
||||
SW[8] = #40000 1'b0;
|
||||
end
|
||||
// SW[ 7 ]
|
||||
initial
|
||||
begin
|
||||
SW[7] = 1'b0;
|
||||
SW[7] = #30000 1'b1;
|
||||
SW[7] = #10000 1'b0;
|
||||
SW[7] = #260000 1'b1;
|
||||
SW[7] = #40000 1'b0;
|
||||
end
|
||||
// SW[ 6 ]
|
||||
initial
|
||||
begin
|
||||
SW[6] = 1'b0;
|
||||
SW[6] = #30000 1'b1;
|
||||
SW[6] = #10000 1'b0;
|
||||
SW[6] = #310000 1'b1;
|
||||
SW[6] = #20000 1'b0;
|
||||
end
|
||||
// SW[ 5 ]
|
||||
initial
|
||||
begin
|
||||
SW[5] = 1'b0;
|
||||
SW[5] = #30000 1'b1;
|
||||
SW[5] = #10000 1'b0;
|
||||
SW[5] = #20000 1'b1;
|
||||
SW[5] = #70000 1'b0;
|
||||
SW[5] = #240000 1'b1;
|
||||
SW[5] = #20000 1'b0;
|
||||
end
|
||||
// SW[ 4 ]
|
||||
initial
|
||||
begin
|
||||
SW[4] = 1'b0;
|
||||
SW[4] = #30000 1'b1;
|
||||
SW[4] = #10000 1'b0;
|
||||
SW[4] = #350000 1'b1;
|
||||
SW[4] = #20000 1'b0;
|
||||
end
|
||||
// SW[ 3 ]
|
||||
initial
|
||||
begin
|
||||
SW[3] = 1'b0;
|
||||
SW[3] = #30000 1'b1;
|
||||
SW[3] = #10000 1'b0;
|
||||
SW[3] = #370000 1'b1;
|
||||
SW[3] = #20000 1'b0;
|
||||
end
|
||||
// SW[ 2 ]
|
||||
initial
|
||||
begin
|
||||
SW[2] = 1'b0;
|
||||
SW[2] = #30000 1'b1;
|
||||
SW[2] = #10000 1'b0;
|
||||
SW[2] = #390000 1'b1;
|
||||
SW[2] = #20000 1'b0;
|
||||
end
|
||||
// SW[ 1 ]
|
||||
initial
|
||||
begin
|
||||
SW[1] = 1'b0;
|
||||
SW[1] = #30000 1'b1;
|
||||
SW[1] = #10000 1'b0;
|
||||
SW[1] = #410000 1'b1;
|
||||
SW[1] = #20000 1'b0;
|
||||
end
|
||||
// SW[ 0 ]
|
||||
initial
|
||||
begin
|
||||
SW[0] = 1'b0;
|
||||
SW[0] = #30000 1'b1;
|
||||
SW[0] = #10000 1'b0;
|
||||
SW[0] = #430000 1'b1;
|
||||
SW[0] = #20000 1'b0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
36
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/transcript
Normal file
36
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/transcript
Normal file
@@ -0,0 +1,36 @@
|
||||
# do Lab1Pt1.do
|
||||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||||
# Start time: 20:02:13 on Feb 25,2021
|
||||
# vlog -work work Lab1Pt1.vo
|
||||
# -- Compiling module Lab1Pt1
|
||||
# -- Compiling module hard_block
|
||||
#
|
||||
# Top level modules:
|
||||
# Lab1Pt1
|
||||
# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||||
# Start time: 20:02:13 on Feb 25,2021
|
||||
# vlog -work work Waveform.vwf.vt
|
||||
# -- Compiling module Lab1Pt1_vlg_vec_tst
|
||||
#
|
||||
# Top level modules:
|
||||
# Lab1Pt1_vlg_vec_tst
|
||||
# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst
|
||||
# Start time: 20:02:14 on Feb 25,2021
|
||||
# Loading work.Lab1Pt1_vlg_vec_tst
|
||||
# Loading work.Lab1Pt1
|
||||
# Loading work.hard_block
|
||||
# ** Warning: (vsim-3017) Lab1Pt1.vo(406): [TFMPC] - Too few port connections. Expected 8, found 7.
|
||||
# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile
|
||||
# ** Warning: (vsim-3722) Lab1Pt1.vo(406): [TFMPC] - Missing connection for port 'clk_dft'.
|
||||
# ** Warning: (vsim-3017) Lab1Pt1.vo(429): [TFMPC] - Too few port connections. Expected 8, found 7.
|
||||
# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile
|
||||
# ** Warning: (vsim-3722) Lab1Pt1.vo(429): [TFMPC] - Missing connection for port 'clk_dft'.
|
||||
# after#24
|
||||
# ** Note: $finish : Waveform.vwf.vt(45)
|
||||
# Time: 1 us Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst
|
||||
# End time: 20:02:14 on Feb 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 4
|
||||
@@ -0,0 +1,142 @@
|
||||
Determining the location of the ModelSim executable...
|
||||
|
||||
Using: c:/intelfpga_lite/16.1/modelsim_ase/win32aloem/
|
||||
|
||||
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
|
||||
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
|
||||
|
||||
**** Generating the ModelSim Testbench ****
|
||||
|
||||
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt"
|
||||
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime EDA Netlist Writer
|
||||
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
|
||||
Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
Info: Your use of Intel Corporation's design tools, logic functions
|
||||
Info: and other software and tools, and its AMPP partner logic
|
||||
Info: functions, and any output files from any of the foregoing
|
||||
Info: (including device programming or simulation files), and any
|
||||
Info: associated documentation or information are expressly subject
|
||||
Info: to the terms and conditions of the Intel Program License
|
||||
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
Info: the Intel MegaCore Function License Agreement, or other
|
||||
Info: applicable license agreement, including, without limitation,
|
||||
Info: that your use is for the sole purpose of programming logic
|
||||
Info: devices manufactured by Intel and sold by Intel or its
|
||||
Info: authorized distributors. Please refer to the applicable
|
||||
Info: agreement for further details.
|
||||
Info: Processing started: Thu Feb 25 20:02:09 2021
|
||||
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Lab1Pt1 -c Lab1Pt1 --vector_source="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf" --testbench_file="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Waveform.vwf.vt"
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
|
||||
Completed successfully.
|
||||
|
||||
Completed successfully.
|
||||
|
||||
**** Generating the functional simulation netlist ****
|
||||
|
||||
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1
|
||||
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime EDA Netlist Writer
|
||||
Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
|
||||
Info: Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
Info: Your use of Intel Corporation's design tools, logic functions
|
||||
Info: and other software and tools, and its AMPP partner logic
|
||||
Info: functions, and any output files from any of the foregoing
|
||||
Info: (including device programming or simulation files), and any
|
||||
Info: associated documentation or information are expressly subject
|
||||
Info: to the terms and conditions of the Intel Program License
|
||||
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
Info: the Intel MegaCore Function License Agreement, or other
|
||||
Info: applicable license agreement, including, without limitation,
|
||||
Info: that your use is for the sole purpose of programming logic
|
||||
Info: devices manufactured by Intel and sold by Intel or its
|
||||
Info: authorized distributors. Please refer to the applicable
|
||||
Info: agreement for further details.
|
||||
Info: Processing started: Thu Feb 25 20:02:10 2021
|
||||
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/" Lab1Pt1 -c Lab1Pt1
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (204019): Generated file Lab1Pt1.vo in folder "C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim//" for EDA simulation tool
|
||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 4641 megabytes
|
||||
Info: Processing ended: Thu Feb 25 20:02:11 2021
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
Completed successfully.
|
||||
|
||||
**** Generating the ModelSim .do script ****
|
||||
|
||||
C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.do generated.
|
||||
|
||||
Completed successfully.
|
||||
|
||||
**** Running the ModelSim simulation ****
|
||||
|
||||
c:/intelfpga_lite/16.1/modelsim_ase/win32aloem//vsim -c -do Lab1Pt1.do
|
||||
|
||||
Reading C:/intelFPGA_lite/16.1/modelsim_ase/tcl/vsim/pref.tcl
|
||||
|
||||
|
||||
# 10.5b
|
||||
|
||||
# do Lab1Pt1.do
|
||||
|
||||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||||
# Start time: 20:02:13 on Feb 25,2021
|
||||
# vlog -work work Lab1Pt1.vo
|
||||
|
||||
# -- Compiling module Lab1Pt1
|
||||
# -- Compiling module hard_block
|
||||
#
|
||||
# Top level modules:
|
||||
# Lab1Pt1
|
||||
# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
|
||||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||||
# Start time: 20:02:13 on Feb 25,2021
|
||||
# vlog -work work Waveform.vwf.vt
|
||||
# -- Compiling module Lab1Pt1_vlg_vec_tst
|
||||
#
|
||||
# Top level modules:
|
||||
# Lab1Pt1_vlg_vec_tst
|
||||
# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
|
||||
# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst
|
||||
# Start time: 20:02:14 on Feb 25,2021
|
||||
# Loading work.Lab1Pt1_vlg_vec_tst
|
||||
# Loading work.Lab1Pt1
|
||||
# Loading work.hard_block
|
||||
# ** Warning: (vsim-3017) Lab1Pt1.vo(406): [TFMPC] - Too few port connections. Expected 8, found 7.
|
||||
# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile
|
||||
# ** Warning: (vsim-3722) Lab1Pt1.vo(406): [TFMPC] - Missing connection for port 'clk_dft'.
|
||||
# ** Warning: (vsim-3017) Lab1Pt1.vo(429): [TFMPC] - Too few port connections. Expected 8, found 7.
|
||||
# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile
|
||||
# ** Warning: (vsim-3722) Lab1Pt1.vo(429): [TFMPC] - Missing connection for port 'clk_dft'.
|
||||
# after#24
|
||||
# ** Note: $finish : Waveform.vwf.vt(45)
|
||||
# Time: 1 us Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst
|
||||
# End time: 20:02:14 on Feb 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 4
|
||||
|
||||
Completed successfully.
|
||||
|
||||
**** Converting ModelSim VCD to vector waveform ****
|
||||
|
||||
Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/Waveform.vwf...
|
||||
|
||||
Reading C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1.msim.vcd...
|
||||
|
||||
Processing channel transitions...
|
||||
|
||||
Writing the resulting VWF to C:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/Lab1Pt1_20210225200214.sim.vwf
|
||||
|
||||
Finished VCD to VWF conversion.
|
||||
|
||||
Completed successfully.
|
||||
|
||||
All completed.
|
||||
75
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_info
Normal file
75
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_info
Normal file
@@ -0,0 +1,75 @@
|
||||
m255
|
||||
K4
|
||||
z2
|
||||
13
|
||||
!s112 1.1
|
||||
!i10d 8192
|
||||
!i10e 25
|
||||
!i10f 100
|
||||
cModel Technology
|
||||
Z0 dC:/Users/anw0044/Desktop/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim
|
||||
vhard_block
|
||||
Z1 !s110 1614304933
|
||||
!i10b 1
|
||||
!s100 DcO78?h1mRCVlg_3oDgmk0
|
||||
IoZd:WG^U6F_U:64<MbAPl1
|
||||
Z2 VDg1SIo80bB@j0V0VzS_@n1
|
||||
R0
|
||||
Z3 w1614304931
|
||||
Z4 8Lab1Pt1.vo
|
||||
Z5 FLab1Pt1.vo
|
||||
L0 473
|
||||
Z6 OV;L;10.5b;63
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z7 !s108 1614304933.000000
|
||||
Z8 !s107 Lab1Pt1.vo|
|
||||
Z9 !s90 -work|work|Lab1Pt1.vo|
|
||||
!i113 1
|
||||
Z10 o-work work
|
||||
Z11 tCvgOpt 0
|
||||
vLab1Pt1
|
||||
R1
|
||||
!i10b 1
|
||||
!s100 jAflPn7=C:T_GzDGN:TR;1
|
||||
I`=OSZ65XNfi>AXFcTmd653
|
||||
R2
|
||||
R0
|
||||
R3
|
||||
R4
|
||||
R5
|
||||
L0 32
|
||||
R6
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R7
|
||||
R8
|
||||
R9
|
||||
!i113 1
|
||||
R10
|
||||
R11
|
||||
n@lab1@pt1
|
||||
vLab1Pt1_vlg_vec_tst
|
||||
R1
|
||||
!i10b 1
|
||||
!s100 7k9eW>3G`@cPjj;45<5M71
|
||||
I6K3e5S;j5kiP]F0?jlZ612
|
||||
R2
|
||||
R0
|
||||
w1614304930
|
||||
8Waveform.vwf.vt
|
||||
FWaveform.vwf.vt
|
||||
L0 30
|
||||
R6
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R7
|
||||
!s107 Waveform.vwf.vt|
|
||||
!s90 -work|work|Waveform.vwf.vt|
|
||||
!i113 1
|
||||
R10
|
||||
R11
|
||||
n@lab1@pt1_vlg_vec_tst
|
||||
BIN
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib.qdb
Normal file
BIN
EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/work/_lib.qdb
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,4 @@
|
||||
m255
|
||||
K4
|
||||
z0
|
||||
cModel Technology
|
||||
Reference in New Issue
Block a user