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Andrew W
2022-08-28 16:12:16 -05:00
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EE203/Noah Woodlee/LAB1/Lab1Part1/simulation/qsim/transcript Normal file
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# do Lab1Pt1.do
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:02:13 on Feb 25,2021
# vlog -work work Lab1Pt1.vo
# -- Compiling module Lab1Pt1
# -- Compiling module hard_block
#
# Top level modules:
# Lab1Pt1
# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 20:02:13 on Feb 25,2021
# vlog -work work Waveform.vwf.vt
# -- Compiling module Lab1Pt1_vlg_vec_tst
#
# Top level modules:
# Lab1Pt1_vlg_vec_tst
# End time: 20:02:13 on Feb 25,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Lab1Pt1_vlg_vec_tst
# Start time: 20:02:14 on Feb 25,2021
# Loading work.Lab1Pt1_vlg_vec_tst
# Loading work.Lab1Pt1
# Loading work.hard_block
# ** Warning: (vsim-3017) Lab1Pt1.vo(406): [TFMPC] - Too few port connections. Expected 8, found 7.
# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: nofile
# ** Warning: (vsim-3722) Lab1Pt1.vo(406): [TFMPC] - Missing connection for port 'clk_dft'.
# ** Warning: (vsim-3017) Lab1Pt1.vo(429): [TFMPC] - Too few port connections. Expected 8, found 7.
# Time: 0 ps Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: nofile
# ** Warning: (vsim-3722) Lab1Pt1.vo(429): [TFMPC] - Missing connection for port 'clk_dft'.
# after#24
# ** Note: $finish : Waveform.vwf.vt(45)
# Time: 1 us Iteration: 0 Instance: /Lab1Pt1_vlg_vec_tst
# End time: 20:02:14 on Feb 25,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 4