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Andrew W
2022-08-28 16:12:16 -05:00
parent 5a2894ed1b
commit 7dabaef6f6
2345 changed files with 1343530 additions and 0 deletions
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top
set_location_assignment PIN_A8 -to LEDR[0]
set_location_assignment PIN_A9 -to LEDR[1]
set_location_assignment PIN_A10 -to LEDR[2]
set_location_assignment PIN_B10 -to LEDR[3]
set_location_assignment PIN_D13 -to LEDR[4]
set_location_assignment PIN_C13 -to LEDR[5]
set_location_assignment PIN_E14 -to LEDR[6]
set_location_assignment PIN_D14 -to LEDR[7]
set_location_assignment PIN_A11 -to LEDR[8]
set_location_assignment PIN_B11 -to LEDR[9]
set_location_assignment PIN_C10 -to SW[0]
set_location_assignment PIN_C11 -to SW[1]
set_location_assignment PIN_D12 -to SW[2]
set_location_assignment PIN_C12 -to SW[3]
set_location_assignment PIN_A12 -to SW[4]
set_location_assignment PIN_B12 -to SW[5]
set_location_assignment PIN_A13 -to SW[6]
set_location_assignment PIN_A14 -to SW[7]
set_location_assignment PIN_B14 -to SW[8]
set_location_assignment PIN_F15 -to SW[9]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top
set_location_assignment PIN_C14 -to HEX0[0]
set_location_assignment PIN_E15 -to HEX0[1]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top
set_location_assignment PIN_C18 -to HEX1[0]
set_location_assignment PIN_D18 -to HEX1[1]
set_location_assignment PIN_C15 -to HEX0[2]
set_location_assignment PIN_C16 -to HEX0[3]
set_location_assignment PIN_E16 -to HEX0[4]
set_location_assignment PIN_D17 -to HEX0[5]
set_location_assignment PIN_C17 -to HEX0[6]
set_location_assignment PIN_E18 -to HEX1[2]
set_location_assignment PIN_B16 -to HEX1[3]
set_location_assignment PIN_A17 -to HEX1[4]
set_location_assignment PIN_A18 -to HEX1[5]
set_location_assignment PIN_B17 -to HEX1[6]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name TOP_LEVEL_ENTITY part1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:13:22 APRIL 16, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "MAX 10 DE10 - Lite"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top
set_global_assignment -name VERILOG_FILE part1.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1619301714813 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1619301714813 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 24 17:01:54 2021 " "Processing started: Sat Apr 24 17:01:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1619301714813 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1619301714813 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off part1 -c part1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off part1 -c part1" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1619301714814 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1619301715159 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1619301717941 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1619301718038 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "355 " "Peak virtual memory: 355 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1619301719290 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 24 17:01:59 2021 " "Processing ended: Sat Apr 24 17:01:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1619301719290 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1619301719290 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1619301719290 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1619301719290 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="part1">
</PROJECT>
</LOG_ROOT>

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v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,0;22;22;0;0;22;22;0;0;0;0;0;0;14;0;0;0;8;14;0;8;0;0;14;0;22;22;22;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,22;0;0;22;22;0;0;22;22;22;22;22;22;8;22;22;22;14;8;22;14;22;22;8;22;0;0;0;22;22,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,

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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Sat Apr 24 16:59:18 2021

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|part1
SW[0] => HEX0.DATAB
SW[0] => HEX0.DATAB
SW[0] => HEX0.DATAB
SW[0] => HEX0.DATAB
SW[0] => HEX0.DATAA
SW[0] => HEX0.DATAA
SW[0] => HEX0.DATAA
SW[0] => HEX0.DATAA
SW[0] => HEX0.DATAA
SW[0] => HEX0.DATAB
SW[0] => HEX0.DATAB
SW[0] => HEX0.DATAA
SW[1] => HEX0.OUTPUTSELECT
SW[1] => HEX0.OUTPUTSELECT
SW[1] => HEX0.OUTPUTSELECT
SW[1] => HEX0.OUTPUTSELECT
SW[1] => HEX0.OUTPUTSELECT
SW[1] => HEX0.OUTPUTSELECT
SW[1] => HEX0.OUTPUTSELECT
SW[1] => HEX0.OUTPUTSELECT
SW[1] => HEX0.DATAA
SW[2] => HEX0.OUTPUTSELECT
SW[2] => HEX0.OUTPUTSELECT
SW[2] => HEX0.OUTPUTSELECT
SW[2] => HEX0.OUTPUTSELECT
SW[2] => HEX0.OUTPUTSELECT
SW[2] => HEX0.OUTPUTSELECT
SW[2] => HEX0.OUTPUTSELECT
SW[3] => HEX0.OUTPUTSELECT
SW[3] => HEX0.OUTPUTSELECT
SW[3] => HEX0.OUTPUTSELECT
SW[3] => HEX0.OUTPUTSELECT
SW[3] => HEX0.OUTPUTSELECT
SW[3] => HEX0.OUTPUTSELECT
SW[3] => HEX0.OUTPUTSELECT
SW[4] => HEX1.DATAB
SW[4] => HEX1.DATAB
SW[4] => HEX1.DATAB
SW[4] => HEX1.DATAB
SW[4] => HEX1.DATAA
SW[4] => HEX1.DATAA
SW[4] => HEX1.DATAA
SW[4] => HEX1.DATAA
SW[4] => HEX1.DATAA
SW[4] => HEX1.DATAB
SW[4] => HEX1.DATAB
SW[4] => HEX1.DATAA
SW[5] => HEX1.OUTPUTSELECT
SW[5] => HEX1.OUTPUTSELECT
SW[5] => HEX1.OUTPUTSELECT
SW[5] => HEX1.OUTPUTSELECT
SW[5] => HEX1.OUTPUTSELECT
SW[5] => HEX1.OUTPUTSELECT
SW[5] => HEX1.OUTPUTSELECT
SW[5] => HEX1.OUTPUTSELECT
SW[5] => HEX1.DATAA
SW[6] => HEX1.OUTPUTSELECT
SW[6] => HEX1.OUTPUTSELECT
SW[6] => HEX1.OUTPUTSELECT
SW[6] => HEX1.OUTPUTSELECT
SW[6] => HEX1.OUTPUTSELECT
SW[6] => HEX1.OUTPUTSELECT
SW[6] => HEX1.OUTPUTSELECT
SW[7] => HEX1.OUTPUTSELECT
SW[7] => HEX1.OUTPUTSELECT
SW[7] => HEX1.OUTPUTSELECT
SW[7] => HEX1.OUTPUTSELECT
SW[7] => HEX1.OUTPUTSELECT
SW[7] => HEX1.OUTPUTSELECT
SW[7] => HEX1.OUTPUTSELECT
HEX0[0] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[1] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[2] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[3] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[4] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[5] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE
HEX0[6] <= HEX0.DB_MAX_OUTPUT_PORT_TYPE
HEX1[0] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE
HEX1[1] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE
HEX1[2] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE
HEX1[3] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE
HEX1[4] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE
HEX1[5] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE
HEX1[6] <= HEX1.DB_MAX_OUTPUT_PORT_TYPE

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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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v1

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v1

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DONE

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start_full_compilation:s:00:00:52
start_analysis_synthesis:s:00:00:17-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:20-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:08-start_full_compilation

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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "HEX0[0]",
"strict" : false
},
{
"name" : "HEX0[1]",
"strict" : false
},
{
"name" : "HEX0[2]",
"strict" : false
},
{
"name" : "HEX0[3]",
"strict" : false
},
{
"name" : "HEX0[4]",
"strict" : false
},
{
"name" : "HEX0[5]",
"strict" : false
},
{
"name" : "HEX0[6]",
"strict" : false
},
{
"name" : "HEX1[0]",
"strict" : false
},
{
"name" : "HEX1[1]",
"strict" : false
},
{
"name" : "HEX1[2]",
"strict" : false
},
{
"name" : "HEX1[3]",
"strict" : false
},
{
"name" : "HEX1[4]",
"strict" : false
},
{
"name" : "HEX1[5]",
"strict" : false
},
{
"name" : "HEX1[6]",
"strict" : false
},
{
"name" : "SW[0]",
"strict" : false
},
{
"name" : "SW[2]",
"strict" : false
},
{
"name" : "SW[1]",
"strict" : false
},
{
"name" : "SW[3]",
"strict" : false
},
{
"name" : "SW[4]",
"strict" : false
},
{
"name" : "SW[6]",
"strict" : false
},
{
"name" : "SW[5]",
"strict" : false
},
{
"name" : "SW[7]",
"strict" : false
}
]
}
]
}

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// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| George Totolos :| 08/22/2016:| Initial Revision
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define ENABLE_ADC_CLOCK
`define ENABLE_CLOCK1
`define ENABLE_CLOCK2
`define ENABLE_SDRAM
`define ENABLE_HEX0
`define ENABLE_HEX1
`define ENABLE_HEX2
`define ENABLE_HEX3
`define ENABLE_HEX4
`define ENABLE_HEX5
`define ENABLE_KEY
`define ENABLE_LED
`define ENABLE_SW
`define ENABLE_VGA
`define ENABLE_ACCELEROMETER
`define ENABLE_ARDUINO
`define ENABLE_GPIO
module DE10_LITE_Golden_Top(
//////////// ADC CLOCK: 3.3-V LVTTL //////////
`ifdef ENABLE_ADC_CLOCK
input ADC_CLK_10,
`endif
//////////// CLOCK 1: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK1
input MAX10_CLK1_50,
`endif
//////////// CLOCK 2: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK2
input MAX10_CLK2_50,
`endif
//////////// SDRAM: 3.3-V LVTTL //////////
`ifdef ENABLE_SDRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
//////////// SEG7: 3.3-V LVTTL //////////
`ifdef ENABLE_HEX0
output [7:0] HEX0,
`endif
`ifdef ENABLE_HEX1
output [7:0] HEX1,
`endif
`ifdef ENABLE_HEX2
output [7:0] HEX2,
`endif
`ifdef ENABLE_HEX3
output [7:0] HEX3,
`endif
`ifdef ENABLE_HEX4
output [7:0] HEX4,
`endif
`ifdef ENABLE_HEX5
output [7:0] HEX5,
`endif
//////////// KEY: 3.3 V SCHMITT TRIGGER //////////
`ifdef ENABLE_KEY
input [1:0] KEY,
`endif
//////////// LED: 3.3-V LVTTL //////////
`ifdef ENABLE_LED
output [9:0] LEDR,
`endif
//////////// SW: 3.3-V LVTTL //////////
`ifdef ENABLE_SW
input [9:0] SW,
`endif
//////////// VGA: 3.3-V LVTTL //////////
`ifdef ENABLE_VGA
output [3:0] VGA_B,
output [3:0] VGA_G,
output VGA_HS,
output [3:0] VGA_R,
output VGA_VS,
`endif
//////////// Accelerometer: 3.3-V LVTTL //////////
`ifdef ENABLE_ACCELEROMETER
output GSENSOR_CS_N,
input [2:1] GSENSOR_INT,
output GSENSOR_SCLK,
inout GSENSOR_SDI,
inout GSENSOR_SDO,
`endif
//////////// Arduino: 3.3-V LVTTL //////////
`ifdef ENABLE_ARDUINO
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`endif
//////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL //////////
`ifdef ENABLE_GPIO
inout [35:0] GPIO
`endif
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule

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DE10_LITE_Golden_Top.v
platform_setup.tcl
filelist.txt

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proc ::setup_project {} {
#============================================================
# Build by Terasic System Builder
#============================================================
set_global_assignment -name FAMILY "MAX 10 FPGA"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0"
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_global_assignment -name SDC_FILE DE10_LITE_Golden_Top.SDC
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
set_location_assignment PIN_N5 -to ADC_CLK_10
set_location_assignment PIN_P11 -to MAX10_CLK1_50
set_location_assignment PIN_N14 -to MAX10_CLK2_50
#============================================================
# SDRAM
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
set_location_assignment PIN_U17 -to DRAM_ADDR[0]
set_location_assignment PIN_W19 -to DRAM_ADDR[1]
set_location_assignment PIN_V18 -to DRAM_ADDR[2]
set_location_assignment PIN_U18 -to DRAM_ADDR[3]
set_location_assignment PIN_U19 -to DRAM_ADDR[4]
set_location_assignment PIN_T18 -to DRAM_ADDR[5]
set_location_assignment PIN_T19 -to DRAM_ADDR[6]
set_location_assignment PIN_R18 -to DRAM_ADDR[7]
set_location_assignment PIN_P18 -to DRAM_ADDR[8]
set_location_assignment PIN_P19 -to DRAM_ADDR[9]
set_location_assignment PIN_T20 -to DRAM_ADDR[10]
set_location_assignment PIN_P20 -to DRAM_ADDR[11]
set_location_assignment PIN_R20 -to DRAM_ADDR[12]
set_location_assignment PIN_T21 -to DRAM_BA[0]
set_location_assignment PIN_T22 -to DRAM_BA[1]
set_location_assignment PIN_U21 -to DRAM_CAS_N
set_location_assignment PIN_N22 -to DRAM_CKE
set_location_assignment PIN_L14 -to DRAM_CLK
set_location_assignment PIN_U20 -to DRAM_CS_N
set_location_assignment PIN_Y21 -to DRAM_DQ[0]
set_location_assignment PIN_Y20 -to DRAM_DQ[1]
set_location_assignment PIN_AA22 -to DRAM_DQ[2]
set_location_assignment PIN_AA21 -to DRAM_DQ[3]
set_location_assignment PIN_Y22 -to DRAM_DQ[4]
set_location_assignment PIN_W22 -to DRAM_DQ[5]
set_location_assignment PIN_W20 -to DRAM_DQ[6]
set_location_assignment PIN_V21 -to DRAM_DQ[7]
set_location_assignment PIN_P21 -to DRAM_DQ[8]
set_location_assignment PIN_J22 -to DRAM_DQ[9]
set_location_assignment PIN_H21 -to DRAM_DQ[10]
set_location_assignment PIN_H22 -to DRAM_DQ[11]
set_location_assignment PIN_G22 -to DRAM_DQ[12]
set_location_assignment PIN_G20 -to DRAM_DQ[13]
set_location_assignment PIN_G19 -to DRAM_DQ[14]
set_location_assignment PIN_F22 -to DRAM_DQ[15]
set_location_assignment PIN_V22 -to DRAM_LDQM
set_location_assignment PIN_U22 -to DRAM_RAS_N
set_location_assignment PIN_J21 -to DRAM_UDQM
set_location_assignment PIN_V20 -to DRAM_WE_N
#============================================================
# SEG7
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
set_location_assignment PIN_C14 -to HEX0[0]
set_location_assignment PIN_E15 -to HEX0[1]
set_location_assignment PIN_C15 -to HEX0[2]
set_location_assignment PIN_C16 -to HEX0[3]
set_location_assignment PIN_E16 -to HEX0[4]
set_location_assignment PIN_D17 -to HEX0[5]
set_location_assignment PIN_C17 -to HEX0[6]
set_location_assignment PIN_D15 -to HEX0[7]
set_location_assignment PIN_C18 -to HEX1[0]
set_location_assignment PIN_D18 -to HEX1[1]
set_location_assignment PIN_E18 -to HEX1[2]
set_location_assignment PIN_B16 -to HEX1[3]
set_location_assignment PIN_A17 -to HEX1[4]
set_location_assignment PIN_A18 -to HEX1[5]
set_location_assignment PIN_B17 -to HEX1[6]
set_location_assignment PIN_A16 -to HEX1[7]
set_location_assignment PIN_B20 -to HEX2[0]
set_location_assignment PIN_A20 -to HEX2[1]
set_location_assignment PIN_B19 -to HEX2[2]
set_location_assignment PIN_A21 -to HEX2[3]
set_location_assignment PIN_B21 -to HEX2[4]
set_location_assignment PIN_C22 -to HEX2[5]
set_location_assignment PIN_B22 -to HEX2[6]
set_location_assignment PIN_A19 -to HEX2[7]
set_location_assignment PIN_F21 -to HEX3[0]
set_location_assignment PIN_E22 -to HEX3[1]
set_location_assignment PIN_E21 -to HEX3[2]
set_location_assignment PIN_C19 -to HEX3[3]
set_location_assignment PIN_C20 -to HEX3[4]
set_location_assignment PIN_D19 -to HEX3[5]
set_location_assignment PIN_E17 -to HEX3[6]
set_location_assignment PIN_D22 -to HEX3[7]
set_location_assignment PIN_F18 -to HEX4[0]
set_location_assignment PIN_E20 -to HEX4[1]
set_location_assignment PIN_E19 -to HEX4[2]
set_location_assignment PIN_J18 -to HEX4[3]
set_location_assignment PIN_H19 -to HEX4[4]
set_location_assignment PIN_F19 -to HEX4[5]
set_location_assignment PIN_F20 -to HEX4[6]
set_location_assignment PIN_F17 -to HEX4[7]
set_location_assignment PIN_J20 -to HEX5[0]
set_location_assignment PIN_K20 -to HEX5[1]
set_location_assignment PIN_L18 -to HEX5[2]
set_location_assignment PIN_N18 -to HEX5[3]
set_location_assignment PIN_M20 -to HEX5[4]
set_location_assignment PIN_N19 -to HEX5[5]
set_location_assignment PIN_N20 -to HEX5[6]
set_location_assignment PIN_L19 -to HEX5[7]
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
set_location_assignment PIN_B8 -to KEY[0]
set_location_assignment PIN_A7 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
set_location_assignment PIN_A8 -to LEDR[0]
set_location_assignment PIN_A9 -to LEDR[1]
set_location_assignment PIN_A10 -to LEDR[2]
set_location_assignment PIN_B10 -to LEDR[3]
set_location_assignment PIN_D13 -to LEDR[4]
set_location_assignment PIN_C13 -to LEDR[5]
set_location_assignment PIN_E14 -to LEDR[6]
set_location_assignment PIN_D14 -to LEDR[7]
set_location_assignment PIN_A11 -to LEDR[8]
set_location_assignment PIN_B11 -to LEDR[9]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
set_location_assignment PIN_C10 -to SW[0]
set_location_assignment PIN_C11 -to SW[1]
set_location_assignment PIN_D12 -to SW[2]
set_location_assignment PIN_C12 -to SW[3]
set_location_assignment PIN_A12 -to SW[4]
set_location_assignment PIN_B12 -to SW[5]
set_location_assignment PIN_A13 -to SW[6]
set_location_assignment PIN_A14 -to SW[7]
set_location_assignment PIN_B14 -to SW[8]
set_location_assignment PIN_F15 -to SW[9]
#============================================================
# VGA
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
set_location_assignment PIN_P1 -to VGA_B[0]
set_location_assignment PIN_T1 -to VGA_B[1]
set_location_assignment PIN_P4 -to VGA_B[2]
set_location_assignment PIN_N2 -to VGA_B[3]
set_location_assignment PIN_W1 -to VGA_G[0]
set_location_assignment PIN_T2 -to VGA_G[1]
set_location_assignment PIN_R2 -to VGA_G[2]
set_location_assignment PIN_R1 -to VGA_G[3]
set_location_assignment PIN_N3 -to VGA_HS
set_location_assignment PIN_AA1 -to VGA_R[0]
set_location_assignment PIN_V1 -to VGA_R[1]
set_location_assignment PIN_Y2 -to VGA_R[2]
set_location_assignment PIN_Y1 -to VGA_R[3]
set_location_assignment PIN_N1 -to VGA_VS
#============================================================
# Accelerometer
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO
set_location_assignment PIN_AB16 -to GSENSOR_CS_N
set_location_assignment PIN_Y14 -to GSENSOR_INT[1]
set_location_assignment PIN_Y13 -to GSENSOR_INT[2]
set_location_assignment PIN_AB15 -to GSENSOR_SCLK
set_location_assignment PIN_V11 -to GSENSOR_SDI
set_location_assignment PIN_V12 -to GSENSOR_SDO
#============================================================
# Arduino
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
set_location_assignment PIN_AB5 -to ARDUINO_IO[0]
set_location_assignment PIN_AB6 -to ARDUINO_IO[1]
set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
set_location_assignment PIN_F16 -to ARDUINO_RESET_N
#============================================================
# GPIO, GPIO connect to GPIO Default
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
set_location_assignment PIN_V10 -to GPIO[0]
set_location_assignment PIN_W10 -to GPIO[1]
set_location_assignment PIN_V9 -to GPIO[2]
set_location_assignment PIN_W9 -to GPIO[3]
set_location_assignment PIN_V8 -to GPIO[4]
set_location_assignment PIN_W8 -to GPIO[5]
set_location_assignment PIN_V7 -to GPIO[6]
set_location_assignment PIN_W7 -to GPIO[7]
set_location_assignment PIN_W6 -to GPIO[8]
set_location_assignment PIN_V5 -to GPIO[9]
set_location_assignment PIN_W5 -to GPIO[10]
set_location_assignment PIN_AA15 -to GPIO[11]
set_location_assignment PIN_AA14 -to GPIO[12]
set_location_assignment PIN_W13 -to GPIO[13]
set_location_assignment PIN_W12 -to GPIO[14]
set_location_assignment PIN_AB13 -to GPIO[15]
set_location_assignment PIN_AB12 -to GPIO[16]
set_location_assignment PIN_Y11 -to GPIO[17]
set_location_assignment PIN_AB11 -to GPIO[18]
set_location_assignment PIN_W11 -to GPIO[19]
set_location_assignment PIN_AB10 -to GPIO[20]
set_location_assignment PIN_AA10 -to GPIO[21]
set_location_assignment PIN_AA9 -to GPIO[22]
set_location_assignment PIN_Y8 -to GPIO[23]
set_location_assignment PIN_AA8 -to GPIO[24]
set_location_assignment PIN_Y7 -to GPIO[25]
set_location_assignment PIN_AA7 -to GPIO[26]
set_location_assignment PIN_Y6 -to GPIO[27]
set_location_assignment PIN_AA6 -to GPIO[28]
set_location_assignment PIN_Y5 -to GPIO[29]
set_location_assignment PIN_AA5 -to GPIO[30]
set_location_assignment PIN_Y4 -to GPIO[31]
set_location_assignment PIN_AB3 -to GPIO[32]
set_location_assignment PIN_Y3 -to GPIO[33]
set_location_assignment PIN_AB2 -to GPIO[34]
set_location_assignment PIN_AA2 -to GPIO[35]
#============================================================
# End of pin assignments by Terasic System Builder
#============================================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
}

6
EE203/Noah Woodlee/Lab2/part1/devkits/DE10_LITE_Golden_Top/qar_info.json Normal file
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{
"common_dir" : "/home/gtotolos/Desktop/max10_de10_lite/Golden_Top/",
"acds_version" : "Version 16.0.0",
"platform" : "linux",
"os" : "Red Hat"
}

8
EE203/Noah Woodlee/Lab2/part1/devkits/readme.txt Normal file
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This devkits directory contains development kit baseline example designs.
HOW TO SETUP PIN ASSIGNMENTS
1) Bring up the Tcl Console panel in Quartus from the View menu --> Utility Windows.
2) Type command 'source platform_setup.tcl' in the Tcl console.
3) Type command 'setup_project' in the Tcl console.
- Running this command will populate all assignments available in the setup_platform.tcl to your project QSF file.

11
EE203/Noah Woodlee/Lab2/part1/incremental_db/README Normal file
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.db_info Normal file
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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Sat Apr 24 16:59:18 2021

BIN
EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.ammdb Normal file
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Binary file not shown.

BIN
EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.cdb Normal file
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Binary file not shown.

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EE203/Noah Woodlee/Lab2/part1/incremental_db/compiled_partitions/part1.root_partition.cmp.dfp Normal file
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v1

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fa8634a97a99232bb4bb1c2e0a376209

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Assembler report for part1
Sat Apr 24 17:01:59 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: part1.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sat Apr 24 17:01:59 2021 ;
; Revision Name ; part1 ;
; Top-level Entity Name ; part1 ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C6GES ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+-----------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+-----------------------------------------------------------------------------------------------+
; File Name ;
+-----------------------------------------------------------------------------------------------+
; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/output_files/part1.sof ;
+-----------------------------------------------------------------------------------------------+
+-------------------------------------+
; Assembler Device Options: part1.sof ;
+----------------+--------------------+
; Option ; Setting ;
+----------------+--------------------+
; JTAG usercode ; 0x002731F7 ;
; Checksum ; 0x002731F7 ;
+----------------+--------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sat Apr 24 17:01:54 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off part1 -c part1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 355 megabytes
Info: Processing ended: Sat Apr 24 17:01:59 2021
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05

1
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Sat Apr 24 17:02:07 2021

1348
EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.rpt Normal file
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EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.smsg Normal file
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Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

18
EE203/Noah Woodlee/Lab2/part1/output_files/part1.fit.summary Normal file
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Fitter Status : Successful - Sat Apr 24 17:01:52 2021
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : part1
Top-level Entity Name : part1
Family : MAX 10
Device : 10M50DAF484C6GES
Timing Models : Preliminary
Total logic elements : 15 / 49,760 ( < 1 % )
Total combinational functions : 15 / 49,760 ( < 1 % )
Dedicated logic registers : 0 / 49,760 ( 0 % )
Total registers : 0
Total pins : 22 / 360 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 1,677,312 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 288 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
UFM blocks : 0 / 1 ( 0 % )
ADC blocks : 0 / 2 ( 0 % )

137
EE203/Noah Woodlee/Lab2/part1/output_files/part1.flow.rpt Normal file
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Flow report for part1
Sat Apr 24 17:02:06 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Sat Apr 24 17:01:59 2021 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; part1 ;
; Top-level Entity Name ; part1 ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C6GES ;
; Timing Models ; Preliminary ;
; Total logic elements ; 15 / 49,760 ( < 1 % ) ;
; Total combinational functions ; 15 / 49,760 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 49,760 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 22 / 360 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 1,677,312 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/24/2021 17:01:18 ;
; Main task ; Compilation ;
; Revision Name ; part1 ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 164639278517.161930167805732 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Lab1Pt1 ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part1_bcd ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part4 ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; part5 ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 393 MB ; 00:00:32 ;
; Fitter ; 00:00:19 ; 1.0 ; 1087 MB ; 00:00:22 ;
; Assembler ; 00:00:05 ; 1.0 ; 355 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 509 MB ; 00:00:06 ;
; Total ; 00:00:44 ; -- ; -- ; 00:01:05 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+-------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+-------------------+------------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+-------------------+------------------+------------+----------------+
; Analysis & Synthesis ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; Fitter ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; Assembler ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
; Timing Analyzer ; TheMachine-SERVER ; Debian GNU/Linux ; 10 ; x86_64 ;
+----------------------+-------------------+------------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1
quartus_fit --read_settings_files=off --write_settings_files=off part1 -c part1
quartus_asm --read_settings_files=off --write_settings_files=off part1 -c part1
quartus_sta part1 -c part1

8
EE203/Noah Woodlee/Lab2/part1/output_files/part1.jdi Normal file
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<sld_project_info>
<project>
<hash md5_digest_80b="bcf3b0e94ca0c617ddf8"/>
</project>
<file_info>
<file device="10M50DAF484C6GES" path="part1.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

384
EE203/Noah Woodlee/Lab2/part1/output_files/part1.map.rpt Normal file
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Analysis & Synthesis report for part1
Sat Apr 24 17:01:32 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Post-Synthesis Netlist Statistics for Top Partition
10. Elapsed Time Per Partition
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Apr 24 17:01:32 2021 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; part1 ;
; Top-level Entity Name ; part1 ;
; Family ; MAX 10 ;
; Total logic elements ; 14 ;
; Total combinational functions ; 14 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 22 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; UFM blocks ; 0 ;
; ADC blocks ; 0 ;
+------------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+
; Device ; 10M50DAF484C6GES ; ;
; Top-level entity name ; part1 ; part1 ;
; Family name ; MAX 10 ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+
; part1.v ; yes ; User Verilog HDL File ; /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/part1.v ; ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------+---------+
+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------------+
; Resource ; Usage ;
+---------------------------------------------+-------------+
; Estimated Total logic elements ; 14 ;
; ; ;
; Total combinational functions ; 14 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 14 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 14 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 22 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; SW[0]~input ;
; Maximum fan-out ; 7 ;
; Total fan-out ; 92 ;
; Average fan-out ; 1.59 ;
+---------------------------------------------+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
; |part1 ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 ; 0 ; 0 ; |part1 ; part1 ; work ;
+----------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 22 ;
; cycloneiii_lcell_comb ; 16 ;
; normal ; 16 ;
; 1 data inputs ; 2 ;
; 4 data inputs ; 14 ;
; ; ;
; Max LUT depth ; 2.00 ;
; Average LUT depth ; 1.50 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:01 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sat Apr 24 17:01:18 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off part1 -c part1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file part1.v
Info (12023): Found entity 1: part1 File: /home/andrew/Storage/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part1/part1.v Line: 1
Info (12127): Elaborating entity "part1" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored
Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored
Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 36 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 8 input pins
Info (21059): Implemented 14 output pins
Info (21061): Implemented 14 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 101 warnings
Info: Peak virtual memory: 394 megabytes
Info: Processing ended: Sat Apr 24 17:01:32 2021
Info: Elapsed time: 00:00:14
Info: Total CPU time (on all processors): 00:00:32

16
EE203/Noah Woodlee/Lab2/part1/output_files/part1.map.summary Normal file
View File

@ -0,0 +1,16 @@
Analysis & Synthesis Status : Successful - Sat Apr 24 17:01:32 2021
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : part1
Top-level Entity Name : part1
Family : MAX 10
Total logic elements : 14
Total combinational functions : 14
Dedicated logic registers : 0
Total registers : 0
Total pins : 22
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0
UFM blocks : 0
ADC blocks : 0

556
EE203/Noah Woodlee/Lab2/part1/output_files/part1.pin Normal file
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@ -0,0 +1,556 @@
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1A: 2.5V
-- Bank 1B: 2.5V
-- Bank 2: 2.5V
-- Bank 3: 2.5V
-- Bank 4: 2.5V
-- Bank 5: 2.5V
-- Bank 6: 2.5V
-- Bank 7: 2.5V
-- Bank 8: 2.5V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
CHIP "part1" ASSIGNED TO AN: 10M50DAF484C6GES
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 :
SW[4] : A12 : input : 2.5 V : : 7 : Y
SW[6] : A13 : input : 2.5 V : : 7 : Y
SW[7] : A14 : input : 2.5 V : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7 :
HEX1[4] : A17 : output : 2.5 V : : 7 : Y
HEX1[5] : A18 : output : 2.5 V : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 6 :
GND : A22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA1 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA2 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 3 :
GND : AA4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
GND : AA18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
GND : AB1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
GND : AB22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 :
GND : B6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7 :
GND : B9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 :
SW[5] : B12 : input : 2.5 V : : 7 : Y
GND : B13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7 :
HEX1[3] : B16 : output : 2.5 V : : 7 : Y
HEX1[6] : B17 : output : 2.5 V : : 7 : Y
GND : B18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 :
SW[0] : C10 : input : 2.5 V : : 7 : Y
SW[1] : C11 : input : 2.5 V : : 7 : Y
SW[3] : C12 : input : 2.5 V : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7 :
HEX0[0] : C14 : output : 2.5 V : : 7 : Y
HEX0[2] : C15 : output : 2.5 V : : 7 : Y
HEX0[3] : C16 : output : 2.5 V : : 7 : Y
HEX0[6] : C17 : output : 2.5 V : : 7 : Y
HEX1[0] : C18 : output : 2.5 V : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 1B :
GND : D4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
GND : D11 : gnd : : : :
SW[2] : D12 : input : 2.5 V : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
GND : D16 : gnd : : : :
HEX0[5] : D17 : output : 2.5 V : : 7 : Y
HEX1[1] : D18 : output : 2.5 V : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 6 :
GND : D20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1B :
GND : E2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1A :
NC : E5 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 :
GND : E7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7 :
HEX0[1] : E15 : output : 2.5 V : : 7 : Y
HEX0[4] : E16 : output : 2.5 V : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 6 :
HEX1[2] : E18 : output : 2.5 V : : 6 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A :
NC : F6 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
~ALTERA_CONF_DONE~ / RESERVED_INPUT : F8 : input : 2.5 V Schmitt Trigger : : 8 : N
VCCIO8 : F9 : power : : 2.5V : 8 :
GND : F10 : gnd : : : :
VCCIO8 : F11 : power : : 2.5V : 8 :
VCCIO7 : F12 : power : : 2.5V : 7 :
GND : F13 : gnd : : : :
VCCIO7 : F14 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1B :
~ALTERA_TCK~ / RESERVED_INPUT : G2 : input : 2.5 V Schmitt Trigger : : 1B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1A :
ANAIN1 : G5 : : : : :
GND : G6 : gnd : : : :
VCCD_PLL3 : G7 : power : : 1.2V : :
GND : G8 : gnd : : : :
~ALTERA_nSTATUS~ / RESERVED_INPUT : G9 : input : 2.5 V Schmitt Trigger : : 8 : N
VCCIO8 : G10 : power : : 2.5V : 8 :
VCCIO8 : G11 : power : : 2.5V : 8 :
VCCIO7 : G12 : power : : 2.5V : 7 :
VCCIO7 : G13 : power : : 2.5V : 7 :
VCCIO7 : G14 : power : : 2.5V : 7 :
GND : G15 : gnd : : : :
VCCD_PLL2 : G16 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 6 :
GND : G18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6 :
GND : G21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H1 : : : : 1B :
~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V Schmitt Trigger : : 1B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1A :
REFGND : H5 : : : : :
ADC_VREF : H6 : : : : :
VCCA_ADC : H7 : power : : 2.5V : :
VCCA3 : H8 : power : : 2.5V : :
~ALTERA_nCONFIG~ / RESERVED_INPUT : H9 : input : 2.5 V Schmitt Trigger : : 8 : N
~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : H10 : input : 2.5 V : : 8 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7 :
VCCA2 : H15 : power : : 2.5V : :
VCCIO6 : H16 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 1B :
GND : J2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1A :
ANAIN2 : J5 : : : : :
GND : J6 : gnd : : : :
VCCINT : J7 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 :
GND : J16 : gnd : : : :
VCCIO6 : J17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 6 :
GND : J19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B :
GND : K3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 1A :
VCCIO1A : K7 : power : : 2.5V : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 1B :
GND : K10 : gnd : : : :
VCC : K11 : power : : 1.2V : :
GND : K12 : gnd : : : :
VCC : K13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 6 :
VCCIO6 : K16 : power : : 2.5V : 6 :
VCCIO6 : K17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1B :
DNU : L3 : : : : :
~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : input : 2.5 V Schmitt Trigger : : 1B : N
GND : L5 : gnd : : : :
VCCIO1A : L6 : power : : 2.5V : 1A :
VCCIO1B : L7 : power : : 2.5V : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 1B :
VCC : L10 : power : : 1.2V : :
VCC : L11 : power : : 1.2V : :
VCC : L12 : power : : 1.2V : :
GND : L13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 6 :
VCCIO6 : L16 : power : : 2.5V : 6 :
GND : L17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6 :
GND : L21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1B :
~ALTERA_TDO~ : M5 : output : 2.5 V : : 1B : N
VCCIO1B : M6 : power : : 2.5V : 1B :
GND : M7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 2 :
GND : M10 : gnd : : : :
VCC : M11 : power : : 1.2V : :
VCC : M12 : power : : 1.2V : :
VCC : M13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M15 : : : : 6 :
GND : M16 : gnd : : : :
VCCIO6 : M17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 6 :
GND : M19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 2 :
VCCIO2 : N6 : power : : 2.5V : 2 :
VCCIO2 : N7 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 2 :
VCC : N10 : power : : 1.2V : :
GND : N11 : gnd : : : :
VCC : N12 : power : : 1.2V : :
GND : N13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 6 :
VCCIO5 : N16 : power : : 2.5V : 5 :
VCCIO6 : N17 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 :
GND : P2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P5 : : : : 2 :
GND : P6 : gnd : : : :
VCCIO2 : P7 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 :
VCCIO5 : P16 : power : : 2.5V : 5 :
GND : P17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
VCCIO2 : R6 : power : : 2.5V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
VCCA1 : R8 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 5 :
VCCIO5 : R16 : power : : 2.5V : 5 :
VCCIO5 : R17 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 5 :
GND : R19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 5 :
GND : R21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
GND : T4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 2 :
VCCD_PLL1 : T7 : power : : 1.2V : :
GND : T8 : gnd : : : :
VCCIO3 : T9 : power : : 2.5V : 3 :
VCCIO3 : T10 : power : : 2.5V : 3 :
VCCIO3 : T11 : power : : 2.5V : 3 :
VCCIO4 : T12 : power : : 2.5V : 4 :
VCCIO4 : T13 : power : : 2.5V : 4 :
GND : T14 : gnd : : : :
VCCA4 : T15 : power : : 2.5V : :
GND : T16 : gnd : : : :
VCCIO5 : T17 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 :
VCCIO3 : U8 : power : : 2.5V : 3 :
VCCIO3 : U9 : power : : 2.5V : 3 :
GND : U10 : gnd : : : :
VCCIO4 : U11 : power : : 2.5V : 4 :
VCCIO4 : U12 : power : : 2.5V : 4 :
GND : U13 : gnd : : : :
VCCIO4 : U14 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4 :
VCCD_PLL4 : U16 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U18 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
GND : V2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 :
GND : V6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 5 :
GND : V19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W19 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5 :
GND : W21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y1 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y2 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3 :
GND : Y9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 4 :
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4 :
GND : Y15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y20 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :

BIN
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<sld_project_info/>

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Timing Analyzer report for part1
Sat Apr 24 17:02:06 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1200mV 85C Model Fmax Summary
6. Slow 1200mV 85C Model Setup Summary
7. Slow 1200mV 85C Model Hold Summary
8. Slow 1200mV 85C Model Recovery Summary
9. Slow 1200mV 85C Model Removal Summary
10. Slow 1200mV 85C Model Minimum Pulse Width Summary
11. Slow 1200mV 85C Model Metastability Summary
12. Slow 1200mV 0C Model Fmax Summary
13. Slow 1200mV 0C Model Setup Summary
14. Slow 1200mV 0C Model Hold Summary
15. Slow 1200mV 0C Model Recovery Summary
16. Slow 1200mV 0C Model Removal Summary
17. Slow 1200mV 0C Model Minimum Pulse Width Summary
18. Slow 1200mV 0C Model Metastability Summary
19. Fast 1200mV 0C Model Setup Summary
20. Fast 1200mV 0C Model Hold Summary
21. Fast 1200mV 0C Model Recovery Summary
22. Fast 1200mV 0C Model Removal Summary
23. Fast 1200mV 0C Model Minimum Pulse Width Summary
24. Fast 1200mV 0C Model Metastability Summary
25. Multicorner Timing Analysis Summary
26. Board Trace Model Assignments
27. Input Transition Times
28. Signal Integrity Metrics (Slow 1200mv 0c Model)
29. Signal Integrity Metrics (Slow 1200mv 85c Model)
30. Signal Integrity Metrics (Fast 1200mv 0c Model)
31. Clock Transfers
32. Report TCCS
33. Report RSKM
34. Unconstrained Paths Summary
35. Unconstrained Input Ports
36. Unconstrained Output Ports
37. Unconstrained Input Ports
38. Unconstrained Output Ports
39. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; part1 ;
; Device Family ; MAX 10 ;
; Device Name ; 10M50DAF484C6GES ;
; Timing Models ; Preliminary ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.01 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; 0.5% ;
+----------------------------+-------------+
----------
; Clocks ;
----------
No clocks to report.
--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+---------------------------------------------------------------------------------+
; Input Transition Times ;
+---------------------+-----------------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------------+-----------------------+-----------------+-----------------+
; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
+---------------------+-----------------------+-----------------+-----------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0607 V ; 0.271 V ; 0.095 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ; 2.32 V ; 1.17e-08 V ; 2.42 V ; -0.0619 V ; 0.272 V ; 0.096 V ; 2.93e-10 s ; 3.92e-10 s ; No ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ; 2.32 V ; 1.97e-08 V ; 2.4 V ; -0.023 V ; 0.201 V ; 0.081 V ; 4.59e-10 s ; 5.51e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.041 V ; 0.145 V ; 0.14 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ; 2.32 V ; 1.79e-06 V ; 2.38 V ; -0.0389 V ; 0.145 V ; 0.139 V ; 4.54e-10 s ; 4.3e-10 s ; No ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ; 2.32 V ; 3.04e-06 V ; 2.37 V ; -0.0115 V ; 0.13 V ; 0.065 V ; 6.31e-10 s ; 6.45e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0396 V ; 0.362 V ; 0.108 V ; 3.11e-10 s ; 4.42e-10 s ; No ; Yes ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 8 ; 8 ;
; Unconstrained Input Port Paths ; 56 ; 56 ;
; Unconstrained Output Ports ; 14 ; 14 ;
; Unconstrained Output Port Paths ; 56 ; 56 ;
+---------------------------------+-------+------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; HEX0[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; HEX1[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sat Apr 24 17:02:00 2021
Info: Command: quartus_sta part1 -c part1
Info: qsta_default_script.tcl version: #1
Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored
Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored
Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored
Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'part1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1200mV 85C Model
Info (332140): No fmax paths to report
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Warning (334000): Timing characteristics of device 10M50DAF484C6GES are preliminary
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1200mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 106 warnings
Info: Peak virtual memory: 509 megabytes
Info: Processing ended: Sat Apr 24 17:02:06 2021
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:06

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------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------
------------------------------------------------------------

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 20:13:22 April 16, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.1"
DATE = "20:13:22 April 16, 2021"
# Revisions
PROJECT_REVISION = "part1"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 20:13:23 April 16, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# part1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name TOP_LEVEL_ENTITY part1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:13:22 APRIL 16, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "MAX 10 DE10 - Lite"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top
set_location_assignment PIN_A8 -to LEDR[0]
set_location_assignment PIN_A9 -to LEDR[1]
set_location_assignment PIN_A10 -to LEDR[2]
set_location_assignment PIN_B10 -to LEDR[3]
set_location_assignment PIN_D13 -to LEDR[4]
set_location_assignment PIN_C13 -to LEDR[5]
set_location_assignment PIN_E14 -to LEDR[6]
set_location_assignment PIN_D14 -to LEDR[7]
set_location_assignment PIN_A11 -to LEDR[8]
set_location_assignment PIN_B11 -to LEDR[9]
set_location_assignment PIN_C10 -to SW[0]
set_location_assignment PIN_C11 -to SW[1]
set_location_assignment PIN_D12 -to SW[2]
set_location_assignment PIN_C12 -to SW[3]
set_location_assignment PIN_A12 -to SW[4]
set_location_assignment PIN_B12 -to SW[5]
set_location_assignment PIN_A13 -to SW[6]
set_location_assignment PIN_A14 -to SW[7]
set_location_assignment PIN_B14 -to SW[8]
set_location_assignment PIN_F15 -to SW[9]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top
set_location_assignment PIN_C14 -to HEX0[0]
set_location_assignment PIN_E15 -to HEX0[1]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top
set_location_assignment PIN_C18 -to HEX1[0]
set_location_assignment PIN_D18 -to HEX1[1]
set_location_assignment PIN_C15 -to HEX0[2]
set_location_assignment PIN_C16 -to HEX0[3]
set_location_assignment PIN_E16 -to HEX0[4]
set_location_assignment PIN_D17 -to HEX0[5]
set_location_assignment PIN_C17 -to HEX0[6]
set_location_assignment PIN_E18 -to HEX1[2]
set_location_assignment PIN_B16 -to HEX1[3]
set_location_assignment PIN_A17 -to HEX1[4]
set_location_assignment PIN_A18 -to HEX1[5]
set_location_assignment PIN_B17 -to HEX1[6]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top
set_global_assignment -name VERILOG_FILE part1.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

49
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@ -0,0 +1,49 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 20:13:23 April 16, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# part1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name TOP_LEVEL_ENTITY part1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:13:22 APRIL 16, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "MAX 10 DE10 - Lite"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

BIN
EE203/Noah Woodlee/Lab2/part1/part1.qws Normal file
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17
EE203/Noah Woodlee/Lab2/part1/part1.v Normal file
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module part1(SW, HEX0, HEX1);
input [7:0] SW;
output [6:0] HEX0, HEX1;
assign HEX0=SW[3]? (SW[0]? 7'b0010_000:7'b0000_000):
(SW[2]? (SW[1]? (SW[0]? 7'b1111_000:7'b0000_010):
(SW[0]? 7'b0010_010:7'b0011_001)):
(SW[1]? (SW[0]? 7'b0110_000:7'b0100_100):
(SW[0]? 7'b1111_001:7'b1000_000)));
assign HEX1=SW[7]? (SW[4]? 7'b0010_000:7'b0000_000):
(SW[6]? (SW[5]? (SW[4]? 7'b1111_000:7'b0000_010):
(SW[4]? 7'b0010_010:7'b0011_001)):
(SW[5]? (SW[4]? 7'b0110_000:7'b0100_100):
(SW[4]? 7'b1111_001:7'b1000_000)));
endmodule

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module part1_bcd(SW, HEX0, HEX1);
input [7:0] SW;
output [6:0] HEX0, HEX1;
assign HEX0=SW[3]? (SW[0]? 7'b0010_000:7'b0000_000):
(SW[2]? (SW[1]? (SW[0]? 7'b1111_000:7'b0000_010):
(SW[0]? 7'b0010_010:7'b0011_001)):
(SW[1]? (SW[0]? 7'b0110_000:7'b0100_100):
(SW[0]? 7'b1111_001:7'b1000_000)));
assign HEX1=SW[7]? (SW[4]? 7'b0010_000:7'b0000_000):
(SW[6]? (SW[5]? (SW[4]? 7'b1111_000:7'b0000_010):
(SW[4]? 7'b0010_010:7'b0011_001)):
(SW[5]? (SW[4]? 7'b0110_000:7'b0100_100):
(SW[4]? 7'b1111_001:7'b1000_000)));
endmodule

808
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@ -0,0 +1,808 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 16:59:18 April 24, 2021
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL -value ENABLE
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?