added more code
This commit is contained in:
Andrew W
@ -0,0 +1,97 @@
|
||||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// *****************************************************************************
|
||||
// This file contains a Verilog test bench with test vectors .The test vectors
|
||||
// are exported from a vector file in the Quartus Waveform Editor and apply to
|
||||
// the top level entity of the current Quartus project .The user can use this
|
||||
// testbench to simulate his design using a third-party simulation tool .
|
||||
// *****************************************************************************
|
||||
// Generated on "04/25/2021 00:26:26"
|
||||
|
||||
// Verilog Test Bench (with test vectors) for design : part3
|
||||
//
|
||||
// Simulation tool : 3rd Party
|
||||
//
|
||||
|
||||
`timescale 1 ps/ 1 ps
|
||||
module part3_vlg_vec_tst();
|
||||
// constants
|
||||
// general purpose registers
|
||||
reg [8:0] SW;
|
||||
// wires
|
||||
wire [4:0] LEDR;
|
||||
|
||||
// assign statements (if any)
|
||||
part3 i1 (
|
||||
// port map - connection between master ports and signals/registers
|
||||
.LEDR(LEDR),
|
||||
.SW(SW)
|
||||
);
|
||||
initial
|
||||
begin
|
||||
#1000000 $finish;
|
||||
end
|
||||
// SW[ 8 ]
|
||||
initial
|
||||
begin
|
||||
SW[8] = 1'b1;
|
||||
SW[8] = #280000 1'b0;
|
||||
end
|
||||
// SW[ 7 ]
|
||||
initial
|
||||
begin
|
||||
SW[7] = 1'b1;
|
||||
SW[7] = #280000 1'b0;
|
||||
end
|
||||
// SW[ 6 ]
|
||||
initial
|
||||
begin
|
||||
SW[6] = 1'b1;
|
||||
SW[6] = #280000 1'b0;
|
||||
end
|
||||
// SW[ 5 ]
|
||||
initial
|
||||
begin
|
||||
SW[5] = 1'b0;
|
||||
end
|
||||
// SW[ 4 ]
|
||||
initial
|
||||
begin
|
||||
SW[4] = 1'b0;
|
||||
end
|
||||
// SW[ 3 ]
|
||||
initial
|
||||
begin
|
||||
SW[3] = 1'b0;
|
||||
end
|
||||
// SW[ 2 ]
|
||||
initial
|
||||
begin
|
||||
SW[2] = 1'b1;
|
||||
SW[2] = #280000 1'b0;
|
||||
end
|
||||
// SW[ 1 ]
|
||||
initial
|
||||
begin
|
||||
SW[1] = 1'b0;
|
||||
end
|
||||
// SW[ 0 ]
|
||||
initial
|
||||
begin
|
||||
SW[0] = 1'b0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,97 @@
|
||||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// *****************************************************************************
|
||||
// This file contains a Verilog test bench with test vectors .The test vectors
|
||||
// are exported from a vector file in the Quartus Waveform Editor and apply to
|
||||
// the top level entity of the current Quartus project .The user can use this
|
||||
// testbench to simulate his design using a third-party simulation tool .
|
||||
// *****************************************************************************
|
||||
// Generated on "04/25/2021 00:51:59"
|
||||
|
||||
// Verilog Test Bench (with test vectors) for design : part3
|
||||
//
|
||||
// Simulation tool : 3rd Party
|
||||
//
|
||||
|
||||
`timescale 1 ps/ 1 ps
|
||||
module part3_vlg_vec_tst();
|
||||
// constants
|
||||
// general purpose registers
|
||||
reg [8:0] SW;
|
||||
// wires
|
||||
wire [4:0] LEDR;
|
||||
|
||||
// assign statements (if any)
|
||||
part3 i1 (
|
||||
// port map - connection between master ports and signals/registers
|
||||
.LEDR(LEDR),
|
||||
.SW(SW)
|
||||
);
|
||||
initial
|
||||
begin
|
||||
#1000000 $finish;
|
||||
end
|
||||
// SW[ 8 ]
|
||||
initial
|
||||
begin
|
||||
SW[8] = 1'b1;
|
||||
SW[8] = #400000 1'b0;
|
||||
end
|
||||
// SW[ 7 ]
|
||||
initial
|
||||
begin
|
||||
SW[7] = 1'b1;
|
||||
SW[7] = #400000 1'b0;
|
||||
end
|
||||
// SW[ 6 ]
|
||||
initial
|
||||
begin
|
||||
SW[6] = 1'b1;
|
||||
SW[6] = #400000 1'b0;
|
||||
end
|
||||
// SW[ 5 ]
|
||||
initial
|
||||
begin
|
||||
SW[5] = 1'b0;
|
||||
end
|
||||
// SW[ 4 ]
|
||||
initial
|
||||
begin
|
||||
SW[4] = 1'b0;
|
||||
end
|
||||
// SW[ 3 ]
|
||||
initial
|
||||
begin
|
||||
SW[3] = 1'b0;
|
||||
end
|
||||
// SW[ 2 ]
|
||||
initial
|
||||
begin
|
||||
SW[2] = 1'b1;
|
||||
SW[2] = #400000 1'b0;
|
||||
end
|
||||
// SW[ 1 ]
|
||||
initial
|
||||
begin
|
||||
SW[1] = 1'b0;
|
||||
end
|
||||
// SW[ 0 ]
|
||||
initial
|
||||
begin
|
||||
SW[0] = 1'b0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,97 @@
|
||||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// *****************************************************************************
|
||||
// This file contains a Verilog test bench with test vectors .The test vectors
|
||||
// are exported from a vector file in the Quartus Waveform Editor and apply to
|
||||
// the top level entity of the current Quartus project .The user can use this
|
||||
// testbench to simulate his design using a third-party simulation tool .
|
||||
// *****************************************************************************
|
||||
// Generated on "04/25/2021 00:09:09"
|
||||
|
||||
// Verilog Test Bench (with test vectors) for design : part3
|
||||
//
|
||||
// Simulation tool : 3rd Party
|
||||
//
|
||||
|
||||
`timescale 1 ps/ 1 ps
|
||||
module part3_vlg_vec_tst();
|
||||
// constants
|
||||
// general purpose registers
|
||||
reg [8:0] SW;
|
||||
// wires
|
||||
wire [4:0] LEDR;
|
||||
|
||||
// assign statements (if any)
|
||||
part3 i1 (
|
||||
// port map - connection between master ports and signals/registers
|
||||
.LEDR(LEDR),
|
||||
.SW(SW)
|
||||
);
|
||||
initial
|
||||
begin
|
||||
#1000000 $finish;
|
||||
end
|
||||
// SW[ 8 ]
|
||||
initial
|
||||
begin
|
||||
SW[8] = 1'b1;
|
||||
SW[8] = #290000 1'b0;
|
||||
end
|
||||
// SW[ 7 ]
|
||||
initial
|
||||
begin
|
||||
SW[7] = 1'b1;
|
||||
SW[7] = #290000 1'b0;
|
||||
end
|
||||
// SW[ 6 ]
|
||||
initial
|
||||
begin
|
||||
SW[6] = 1'b1;
|
||||
SW[6] = #290000 1'b0;
|
||||
end
|
||||
// SW[ 5 ]
|
||||
initial
|
||||
begin
|
||||
SW[5] = 1'b0;
|
||||
end
|
||||
// SW[ 4 ]
|
||||
initial
|
||||
begin
|
||||
SW[4] = 1'b0;
|
||||
end
|
||||
// SW[ 3 ]
|
||||
initial
|
||||
begin
|
||||
SW[3] = 1'b0;
|
||||
end
|
||||
// SW[ 2 ]
|
||||
initial
|
||||
begin
|
||||
SW[2] = 1'b1;
|
||||
SW[2] = #290000 1'b0;
|
||||
end
|
||||
// SW[ 1 ]
|
||||
initial
|
||||
begin
|
||||
SW[1] = 1'b0;
|
||||
end
|
||||
// SW[ 0 ]
|
||||
initial
|
||||
begin
|
||||
SW[0] = 1'b0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,97 @@
|
||||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// *****************************************************************************
|
||||
// This file contains a Verilog test bench with test vectors .The test vectors
|
||||
// are exported from a vector file in the Quartus Waveform Editor and apply to
|
||||
// the top level entity of the current Quartus project .The user can use this
|
||||
// testbench to simulate his design using a third-party simulation tool .
|
||||
// *****************************************************************************
|
||||
// Generated on "04/25/2021 00:16:46"
|
||||
|
||||
// Verilog Test Bench (with test vectors) for design : part3
|
||||
//
|
||||
// Simulation tool : 3rd Party
|
||||
//
|
||||
|
||||
`timescale 1 ps/ 1 ps
|
||||
module part3_vlg_vec_tst();
|
||||
// constants
|
||||
// general purpose registers
|
||||
reg [8:0] SW;
|
||||
// wires
|
||||
wire [4:0] LEDR;
|
||||
|
||||
// assign statements (if any)
|
||||
part3 i1 (
|
||||
// port map - connection between master ports and signals/registers
|
||||
.LEDR(LEDR),
|
||||
.SW(SW)
|
||||
);
|
||||
initial
|
||||
begin
|
||||
#1000000 $finish;
|
||||
end
|
||||
// SW[ 8 ]
|
||||
initial
|
||||
begin
|
||||
SW[8] = 1'b1;
|
||||
SW[8] = #440000 1'b0;
|
||||
end
|
||||
// SW[ 7 ]
|
||||
initial
|
||||
begin
|
||||
SW[7] = 1'b1;
|
||||
SW[7] = #440000 1'b0;
|
||||
end
|
||||
// SW[ 6 ]
|
||||
initial
|
||||
begin
|
||||
SW[6] = 1'b1;
|
||||
SW[6] = #440000 1'b0;
|
||||
end
|
||||
// SW[ 5 ]
|
||||
initial
|
||||
begin
|
||||
SW[5] = 1'b0;
|
||||
end
|
||||
// SW[ 4 ]
|
||||
initial
|
||||
begin
|
||||
SW[4] = 1'b0;
|
||||
end
|
||||
// SW[ 3 ]
|
||||
initial
|
||||
begin
|
||||
SW[3] = 1'b0;
|
||||
end
|
||||
// SW[ 2 ]
|
||||
initial
|
||||
begin
|
||||
SW[2] = 1'b1;
|
||||
SW[2] = #440000 1'b0;
|
||||
end
|
||||
// SW[ 1 ]
|
||||
initial
|
||||
begin
|
||||
SW[1] = 1'b0;
|
||||
end
|
||||
// SW[ 0 ]
|
||||
initial
|
||||
begin
|
||||
SW[0] = 1'b0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -0,0 +1,97 @@
|
||||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// *****************************************************************************
|
||||
// This file contains a Verilog test bench with test vectors .The test vectors
|
||||
// are exported from a vector file in the Quartus Waveform Editor and apply to
|
||||
// the top level entity of the current Quartus project .The user can use this
|
||||
// testbench to simulate his design using a third-party simulation tool .
|
||||
// *****************************************************************************
|
||||
// Generated on "04/25/2021 00:19:15"
|
||||
|
||||
// Verilog Test Bench (with test vectors) for design : part3
|
||||
//
|
||||
// Simulation tool : 3rd Party
|
||||
//
|
||||
|
||||
`timescale 1 ps/ 1 ps
|
||||
module part3_vlg_vec_tst();
|
||||
// constants
|
||||
// general purpose registers
|
||||
reg [8:0] SW;
|
||||
// wires
|
||||
wire [4:0] LEDR;
|
||||
|
||||
// assign statements (if any)
|
||||
part3 i1 (
|
||||
// port map - connection between master ports and signals/registers
|
||||
.LEDR(LEDR),
|
||||
.SW(SW)
|
||||
);
|
||||
initial
|
||||
begin
|
||||
#1000000 $finish;
|
||||
end
|
||||
// SW[ 8 ]
|
||||
initial
|
||||
begin
|
||||
SW[8] = 1'b1;
|
||||
SW[8] = #360000 1'b0;
|
||||
end
|
||||
// SW[ 7 ]
|
||||
initial
|
||||
begin
|
||||
SW[7] = 1'b1;
|
||||
SW[7] = #360000 1'b0;
|
||||
end
|
||||
// SW[ 6 ]
|
||||
initial
|
||||
begin
|
||||
SW[6] = 1'b1;
|
||||
SW[6] = #360000 1'b0;
|
||||
end
|
||||
// SW[ 5 ]
|
||||
initial
|
||||
begin
|
||||
SW[5] = 1'b0;
|
||||
end
|
||||
// SW[ 4 ]
|
||||
initial
|
||||
begin
|
||||
SW[4] = 1'b0;
|
||||
end
|
||||
// SW[ 3 ]
|
||||
initial
|
||||
begin
|
||||
SW[3] = 1'b0;
|
||||
end
|
||||
// SW[ 2 ]
|
||||
initial
|
||||
begin
|
||||
SW[2] = 1'b1;
|
||||
SW[2] = #360000 1'b0;
|
||||
end
|
||||
// SW[ 1 ]
|
||||
initial
|
||||
begin
|
||||
SW[1] = 1'b0;
|
||||
end
|
||||
// SW[ 0 ]
|
||||
initial
|
||||
begin
|
||||
SW[0] = 1'b0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
17
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.do
Normal file
17
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.do
Normal file
@ -0,0 +1,17 @@
|
||||
onerror {exit -code 1}
|
||||
vlib work
|
||||
vlog -work work part3.vo
|
||||
vlog -work work Waveform1.vwf.vt
|
||||
vsim -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst
|
||||
vcd file -direction part3.msim.vcd
|
||||
vcd add -internal part3_vlg_vec_tst/*
|
||||
vcd add -internal part3_vlg_vec_tst/i1/*
|
||||
proc simTimestamp {} {
|
||||
echo "Simulation time: $::now ps"
|
||||
if { [string equal running [runStatus]] } {
|
||||
after 2500 simTimestamp
|
||||
}
|
||||
}
|
||||
after 2500 simTimestamp
|
||||
run -all
|
||||
quit -f
|
||||
124
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.msim.vcd
Normal file
124
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.msim.vcd
Normal file
@ -0,0 +1,124 @@
|
||||
$comment
|
||||
File created using the following command:
|
||||
vcd file part3.msim.vcd -direction
|
||||
$end
|
||||
$date
|
||||
Sun Apr 25 00:52:04 2021
|
||||
$end
|
||||
$version
|
||||
ModelSim Version 2020.1
|
||||
$end
|
||||
$timescale
|
||||
1ps
|
||||
$end
|
||||
|
||||
$scope module part3_vlg_vec_tst $end
|
||||
$var reg 9 ! SW [8:0] $end
|
||||
$var wire 1 " LEDR [4] $end
|
||||
$var wire 1 # LEDR [3] $end
|
||||
$var wire 1 $ LEDR [2] $end
|
||||
$var wire 1 % LEDR [1] $end
|
||||
$var wire 1 & LEDR [0] $end
|
||||
|
||||
$scope module i1 $end
|
||||
$var wire 1 ' gnd $end
|
||||
$var wire 1 ( vcc $end
|
||||
$var wire 1 ) unknown $end
|
||||
$var tri1 1 * devclrn $end
|
||||
$var tri1 1 + devpor $end
|
||||
$var tri1 1 , devoe $end
|
||||
$var wire 1 - ~QUARTUS_CREATED_GND~I_combout $end
|
||||
$var wire 1 . ~QUARTUS_CREATED_UNVM~~busy $end
|
||||
$var wire 1 / ~QUARTUS_CREATED_ADC1~~eoc $end
|
||||
$var wire 1 0 ~QUARTUS_CREATED_ADC2~~eoc $end
|
||||
$var wire 1 1 LEDR[0]~output_o $end
|
||||
$var wire 1 2 LEDR[1]~output_o $end
|
||||
$var wire 1 3 LEDR[2]~output_o $end
|
||||
$var wire 1 4 LEDR[3]~output_o $end
|
||||
$var wire 1 5 LEDR[4]~output_o $end
|
||||
$var wire 1 6 SW[4]~input_o $end
|
||||
$var wire 1 7 SW[0]~input_o $end
|
||||
$var wire 1 8 SW[8]~input_o $end
|
||||
$var wire 1 9 A0|x1~combout $end
|
||||
$var wire 1 : SW[5]~input_o $end
|
||||
$var wire 1 ; SW[1]~input_o $end
|
||||
$var wire 1 < A0|COUT~0_combout $end
|
||||
$var wire 1 = A1|x1~combout $end
|
||||
$var wire 1 > SW[2]~input_o $end
|
||||
$var wire 1 ? SW[6]~input_o $end
|
||||
$var wire 1 @ A2|x0~combout $end
|
||||
$var wire 1 A A2|x1~combout $end
|
||||
$var wire 1 B A2|COUT~2_combout $end
|
||||
$var wire 1 C A2|COUT~3_combout $end
|
||||
$var wire 1 D SW[3]~input_o $end
|
||||
$var wire 1 E SW[7]~input_o $end
|
||||
$var wire 1 F A3|x1~combout $end
|
||||
$var wire 1 G A3|COUT~0_combout $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b111000100 !
|
||||
1&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
1"
|
||||
0'
|
||||
1(
|
||||
x)
|
||||
1*
|
||||
1+
|
||||
1,
|
||||
0-
|
||||
z.
|
||||
z/
|
||||
z0
|
||||
11
|
||||
02
|
||||
03
|
||||
04
|
||||
15
|
||||
06
|
||||
07
|
||||
18
|
||||
19
|
||||
0:
|
||||
0;
|
||||
0<
|
||||
0=
|
||||
1>
|
||||
1?
|
||||
0@
|
||||
0A
|
||||
0B
|
||||
1C
|
||||
0D
|
||||
1E
|
||||
0F
|
||||
1G
|
||||
$end
|
||||
#400000
|
||||
b11000100 !
|
||||
b1000100 !
|
||||
b100 !
|
||||
b0 !
|
||||
08
|
||||
0E
|
||||
0?
|
||||
0>
|
||||
0C
|
||||
09
|
||||
0G
|
||||
1F
|
||||
14
|
||||
05
|
||||
01
|
||||
0&
|
||||
0"
|
||||
1#
|
||||
0F
|
||||
04
|
||||
0#
|
||||
#1000000
|
||||
1
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.sft
Normal file
1
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.sft
Normal file
@ -0,0 +1 @@
|
||||
set tool_name "ModelSim-Altera (Verilog)"
|
||||
582
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.vo
Normal file
582
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/part3.vo
Normal file
@ -0,0 +1,582 @@
|
||||
// Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and any partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details, at
|
||||
// https://fpgasoftware.intel.com/eula.
|
||||
|
||||
// VENDOR "Altera"
|
||||
// PROGRAM "Quartus Prime"
|
||||
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
|
||||
// DATE "04/25/2021 00:52:01"
|
||||
|
||||
//
|
||||
// Device: Altera 10M50DAF484C6GES Package FBGA484
|
||||
//
|
||||
|
||||
//
|
||||
// This Verilog file should be used for ModelSim-Altera (Verilog) only
|
||||
//
|
||||
|
||||
`timescale 1 ps/ 1 ps
|
||||
|
||||
module part3 (
|
||||
SW,
|
||||
LEDR);
|
||||
input [8:0] SW;
|
||||
output [4:0] LEDR;
|
||||
|
||||
// Design Ports Information
|
||||
// LEDR[0] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[2] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[3] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// LEDR[4] => Location: PIN_D13, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[8] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[0] => Location: PIN_C10, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[4] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[1] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[5] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[2] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[6] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[3] => Location: PIN_C12, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// SW[7] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default
|
||||
|
||||
|
||||
wire gnd;
|
||||
wire vcc;
|
||||
wire unknown;
|
||||
|
||||
assign gnd = 1'b0;
|
||||
assign vcc = 1'b1;
|
||||
assign unknown = 1'bx;
|
||||
|
||||
tri1 devclrn;
|
||||
tri1 devpor;
|
||||
tri1 devoe;
|
||||
wire \~QUARTUS_CREATED_GND~I_combout ;
|
||||
wire \~QUARTUS_CREATED_UNVM~~busy ;
|
||||
wire \~QUARTUS_CREATED_ADC1~~eoc ;
|
||||
wire \~QUARTUS_CREATED_ADC2~~eoc ;
|
||||
wire \LEDR[0]~output_o ;
|
||||
wire \LEDR[1]~output_o ;
|
||||
wire \LEDR[2]~output_o ;
|
||||
wire \LEDR[3]~output_o ;
|
||||
wire \LEDR[4]~output_o ;
|
||||
wire \SW[4]~input_o ;
|
||||
wire \SW[0]~input_o ;
|
||||
wire \SW[8]~input_o ;
|
||||
wire \A0|x1~combout ;
|
||||
wire \SW[5]~input_o ;
|
||||
wire \SW[1]~input_o ;
|
||||
wire \A0|COUT~0_combout ;
|
||||
wire \A1|x1~combout ;
|
||||
wire \SW[2]~input_o ;
|
||||
wire \SW[6]~input_o ;
|
||||
wire \A2|x0~combout ;
|
||||
wire \A2|x1~combout ;
|
||||
wire \A2|COUT~2_combout ;
|
||||
wire \A2|COUT~3_combout ;
|
||||
wire \SW[3]~input_o ;
|
||||
wire \SW[7]~input_o ;
|
||||
wire \A3|x1~combout ;
|
||||
wire \A3|COUT~0_combout ;
|
||||
|
||||
|
||||
hard_block auto_generated_inst(
|
||||
.devpor(devpor),
|
||||
.devclrn(devclrn),
|
||||
.devoe(devoe));
|
||||
|
||||
// Location: LCCOMB_X44_Y41_N16
|
||||
fiftyfivenm_lcell_comb \~QUARTUS_CREATED_GND~I (
|
||||
// Equation(s):
|
||||
// \~QUARTUS_CREATED_GND~I_combout = GND
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(gnd),
|
||||
.datac(gnd),
|
||||
.datad(gnd),
|
||||
.cin(gnd),
|
||||
.combout(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_GND~I .lut_mask = 16'h0000;
|
||||
defparam \~QUARTUS_CREATED_GND~I .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X46_Y54_N2
|
||||
fiftyfivenm_io_obuf \LEDR[0]~output (
|
||||
.i(\A0|x1~combout ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[0]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[0]~output .bus_hold = "false";
|
||||
defparam \LEDR[0]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X46_Y54_N23
|
||||
fiftyfivenm_io_obuf \LEDR[1]~output (
|
||||
.i(\A1|x1~combout ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[1]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[1]~output .bus_hold = "false";
|
||||
defparam \LEDR[1]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X51_Y54_N16
|
||||
fiftyfivenm_io_obuf \LEDR[2]~output (
|
||||
.i(\A2|x1~combout ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[2]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[2]~output .bus_hold = "false";
|
||||
defparam \LEDR[2]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X46_Y54_N9
|
||||
fiftyfivenm_io_obuf \LEDR[3]~output (
|
||||
.i(\A3|x1~combout ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[3]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[3]~output .bus_hold = "false";
|
||||
defparam \LEDR[3]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOOBUF_X56_Y54_N30
|
||||
fiftyfivenm_io_obuf \LEDR[4]~output (
|
||||
.i(\A3|COUT~0_combout ),
|
||||
.oe(vcc),
|
||||
.seriesterminationcontrol(16'b0000000000000000),
|
||||
.devoe(devoe),
|
||||
.o(\LEDR[4]~output_o ),
|
||||
.obar());
|
||||
// synopsys translate_off
|
||||
defparam \LEDR[4]~output .bus_hold = "false";
|
||||
defparam \LEDR[4]~output .open_drain_output = "false";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X54_Y54_N22
|
||||
fiftyfivenm_io_ibuf \SW[4]~input (
|
||||
.i(SW[4]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[4]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[4]~input .bus_hold = "false";
|
||||
defparam \SW[4]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[4]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X51_Y54_N29
|
||||
fiftyfivenm_io_ibuf \SW[0]~input (
|
||||
.i(SW[0]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[0]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[0]~input .bus_hold = "false";
|
||||
defparam \SW[0]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[0]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X56_Y54_N1
|
||||
fiftyfivenm_io_ibuf \SW[8]~input (
|
||||
.i(SW[8]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[8]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[8]~input .bus_hold = "false";
|
||||
defparam \SW[8]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[8]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N24
|
||||
fiftyfivenm_lcell_comb \A0|x1 (
|
||||
// Equation(s):
|
||||
// \A0|x1~combout = \SW[4]~input_o $ (\SW[0]~input_o $ (\SW[8]~input_o ))
|
||||
|
||||
.dataa(\SW[4]~input_o ),
|
||||
.datab(\SW[0]~input_o ),
|
||||
.datac(gnd),
|
||||
.datad(\SW[8]~input_o ),
|
||||
.cin(gnd),
|
||||
.combout(\A0|x1~combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A0|x1 .lut_mask = 16'h9966;
|
||||
defparam \A0|x1 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X49_Y54_N1
|
||||
fiftyfivenm_io_ibuf \SW[5]~input (
|
||||
.i(SW[5]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[5]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[5]~input .bus_hold = "false";
|
||||
defparam \SW[5]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[5]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X51_Y54_N22
|
||||
fiftyfivenm_io_ibuf \SW[1]~input (
|
||||
.i(SW[1]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[1]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[1]~input .bus_hold = "false";
|
||||
defparam \SW[1]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[1]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N26
|
||||
fiftyfivenm_lcell_comb \A0|COUT~0 (
|
||||
// Equation(s):
|
||||
// \A0|COUT~0_combout = (\SW[4]~input_o & ((\SW[0]~input_o ) # (\SW[8]~input_o ))) # (!\SW[4]~input_o & (\SW[0]~input_o & \SW[8]~input_o ))
|
||||
|
||||
.dataa(\SW[4]~input_o ),
|
||||
.datab(\SW[0]~input_o ),
|
||||
.datac(gnd),
|
||||
.datad(\SW[8]~input_o ),
|
||||
.cin(gnd),
|
||||
.combout(\A0|COUT~0_combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A0|COUT~0 .lut_mask = 16'hEE88;
|
||||
defparam \A0|COUT~0 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N12
|
||||
fiftyfivenm_lcell_comb \A1|x1 (
|
||||
// Equation(s):
|
||||
// \A1|x1~combout = \SW[5]~input_o $ (\SW[1]~input_o $ (\A0|COUT~0_combout ))
|
||||
|
||||
.dataa(\SW[5]~input_o ),
|
||||
.datab(\SW[1]~input_o ),
|
||||
.datac(\A0|COUT~0_combout ),
|
||||
.datad(gnd),
|
||||
.cin(gnd),
|
||||
.combout(\A1|x1~combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A1|x1 .lut_mask = 16'h9696;
|
||||
defparam \A1|x1 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X51_Y54_N1
|
||||
fiftyfivenm_io_ibuf \SW[2]~input (
|
||||
.i(SW[2]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[2]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[2]~input .bus_hold = "false";
|
||||
defparam \SW[2]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[2]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X54_Y54_N15
|
||||
fiftyfivenm_io_ibuf \SW[6]~input (
|
||||
.i(SW[6]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[6]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[6]~input .bus_hold = "false";
|
||||
defparam \SW[6]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[6]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N22
|
||||
fiftyfivenm_lcell_comb \A2|x0 (
|
||||
// Equation(s):
|
||||
// \A2|x0~combout = \SW[2]~input_o $ (\SW[6]~input_o )
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(gnd),
|
||||
.datac(\SW[2]~input_o ),
|
||||
.datad(\SW[6]~input_o ),
|
||||
.cin(gnd),
|
||||
.combout(\A2|x0~combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A2|x0 .lut_mask = 16'h0FF0;
|
||||
defparam \A2|x0 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N16
|
||||
fiftyfivenm_lcell_comb \A2|x1 (
|
||||
// Equation(s):
|
||||
// \A2|x1~combout = \A2|x0~combout $ (((\SW[1]~input_o & ((\A0|COUT~0_combout ) # (\SW[5]~input_o ))) # (!\SW[1]~input_o & (\A0|COUT~0_combout & \SW[5]~input_o ))))
|
||||
|
||||
.dataa(\A2|x0~combout ),
|
||||
.datab(\SW[1]~input_o ),
|
||||
.datac(\A0|COUT~0_combout ),
|
||||
.datad(\SW[5]~input_o ),
|
||||
.cin(gnd),
|
||||
.combout(\A2|x1~combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A2|x1 .lut_mask = 16'h566A;
|
||||
defparam \A2|x1 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N10
|
||||
fiftyfivenm_lcell_comb \A2|COUT~2 (
|
||||
// Equation(s):
|
||||
// \A2|COUT~2_combout = (\A2|x0~combout & ((\SW[1]~input_o & ((\A0|COUT~0_combout ) # (\SW[5]~input_o ))) # (!\SW[1]~input_o & (\A0|COUT~0_combout & \SW[5]~input_o ))))
|
||||
|
||||
.dataa(\A2|x0~combout ),
|
||||
.datab(\SW[1]~input_o ),
|
||||
.datac(\A0|COUT~0_combout ),
|
||||
.datad(\SW[5]~input_o ),
|
||||
.cin(gnd),
|
||||
.combout(\A2|COUT~2_combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A2|COUT~2 .lut_mask = 16'hA880;
|
||||
defparam \A2|COUT~2 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N0
|
||||
fiftyfivenm_lcell_comb \A2|COUT~3 (
|
||||
// Equation(s):
|
||||
// \A2|COUT~3_combout = (\A2|COUT~2_combout ) # ((\SW[2]~input_o & \SW[6]~input_o ))
|
||||
|
||||
.dataa(\A2|COUT~2_combout ),
|
||||
.datab(gnd),
|
||||
.datac(\SW[2]~input_o ),
|
||||
.datad(\SW[6]~input_o ),
|
||||
.cin(gnd),
|
||||
.combout(\A2|COUT~3_combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A2|COUT~3 .lut_mask = 16'hFAAA;
|
||||
defparam \A2|COUT~3 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X54_Y54_N29
|
||||
fiftyfivenm_io_ibuf \SW[3]~input (
|
||||
.i(SW[3]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[3]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[3]~input .bus_hold = "false";
|
||||
defparam \SW[3]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[3]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: IOIBUF_X58_Y54_N29
|
||||
fiftyfivenm_io_ibuf \SW[7]~input (
|
||||
.i(SW[7]),
|
||||
.ibar(gnd),
|
||||
.nsleep(vcc),
|
||||
.o(\SW[7]~input_o ));
|
||||
// synopsys translate_off
|
||||
defparam \SW[7]~input .bus_hold = "false";
|
||||
defparam \SW[7]~input .listen_to_nsleep_signal = "false";
|
||||
defparam \SW[7]~input .simulate_z_as = "z";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N20
|
||||
fiftyfivenm_lcell_comb \A3|x1 (
|
||||
// Equation(s):
|
||||
// \A3|x1~combout = \A2|COUT~3_combout $ (\SW[3]~input_o $ (\SW[7]~input_o ))
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(\A2|COUT~3_combout ),
|
||||
.datac(\SW[3]~input_o ),
|
||||
.datad(\SW[7]~input_o ),
|
||||
.cin(gnd),
|
||||
.combout(\A3|x1~combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A3|x1 .lut_mask = 16'hC33C;
|
||||
defparam \A3|x1 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: LCCOMB_X51_Y53_N6
|
||||
fiftyfivenm_lcell_comb \A3|COUT~0 (
|
||||
// Equation(s):
|
||||
// \A3|COUT~0_combout = (\A2|COUT~3_combout & ((\SW[3]~input_o ) # (\SW[7]~input_o ))) # (!\A2|COUT~3_combout & (\SW[3]~input_o & \SW[7]~input_o ))
|
||||
|
||||
.dataa(gnd),
|
||||
.datab(\A2|COUT~3_combout ),
|
||||
.datac(\SW[3]~input_o ),
|
||||
.datad(\SW[7]~input_o ),
|
||||
.cin(gnd),
|
||||
.combout(\A3|COUT~0_combout ),
|
||||
.cout());
|
||||
// synopsys translate_off
|
||||
defparam \A3|COUT~0 .lut_mask = 16'hFCC0;
|
||||
defparam \A3|COUT~0 .sum_lutc_input = "datac";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: UNVM_X0_Y40_N40
|
||||
fiftyfivenm_unvm \~QUARTUS_CREATED_UNVM~ (
|
||||
.arclk(vcc),
|
||||
.arshft(vcc),
|
||||
.drclk(vcc),
|
||||
.drshft(vcc),
|
||||
.drdin(vcc),
|
||||
.nprogram(vcc),
|
||||
.nerase(vcc),
|
||||
.nosc_ena(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.par_en(vcc),
|
||||
.xe_ye(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.se(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.ardin(23'b11111111111111111111111),
|
||||
.busy(\~QUARTUS_CREATED_UNVM~~busy ),
|
||||
.osc(),
|
||||
.bgpbusy(),
|
||||
.sp_pass(),
|
||||
.se_pass(),
|
||||
.drdout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_end_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .addr_range1_offset = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_end_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .addr_range2_offset = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .addr_range3_offset = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .is_compressed_image = "false";
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .is_dual_boot = "false";
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .is_eram_skip = "false";
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .max_ufm_valid_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .max_valid_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .min_ufm_valid_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .min_valid_addr = -1;
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .part_name = "quartus_created_unvm";
|
||||
defparam \~QUARTUS_CREATED_UNVM~ .reserve_block = "true";
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: ADCBLOCK_X43_Y52_N0
|
||||
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC1~ (
|
||||
.soc(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.usr_pwd(vcc),
|
||||
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.clkin_from_pll_c0(gnd),
|
||||
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
|
||||
.eoc(\~QUARTUS_CREATED_ADC1~~eoc ),
|
||||
.dout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .analog_input_pin_mask = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .clkdiv = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .device_partname_fivechar_prefix = "none";
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .is_this_first_or_second_adc = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .prescalar = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .pwd = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .refsel = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .reserve_block = "true";
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .testbits = 66;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .tsclkdiv = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC1~ .tsclksel = 0;
|
||||
// synopsys translate_on
|
||||
|
||||
// Location: ADCBLOCK_X43_Y51_N0
|
||||
fiftyfivenm_adcblock \~QUARTUS_CREATED_ADC2~ (
|
||||
.soc(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.usr_pwd(vcc),
|
||||
.tsen(\~QUARTUS_CREATED_GND~I_combout ),
|
||||
.clkin_from_pll_c0(gnd),
|
||||
.chsel({\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout ,\~QUARTUS_CREATED_GND~I_combout }),
|
||||
.eoc(\~QUARTUS_CREATED_ADC2~~eoc ),
|
||||
.dout());
|
||||
// synopsys translate_off
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .analog_input_pin_mask = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .clkdiv = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .device_partname_fivechar_prefix = "none";
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .is_this_first_or_second_adc = 2;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .prescalar = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .pwd = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .refsel = 0;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .reserve_block = "true";
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .testbits = 66;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .tsclkdiv = 1;
|
||||
defparam \~QUARTUS_CREATED_ADC2~ .tsclksel = 0;
|
||||
// synopsys translate_on
|
||||
|
||||
assign LEDR[0] = \LEDR[0]~output_o ;
|
||||
|
||||
assign LEDR[1] = \LEDR[1]~output_o ;
|
||||
|
||||
assign LEDR[2] = \LEDR[2]~output_o ;
|
||||
|
||||
assign LEDR[3] = \LEDR[3]~output_o ;
|
||||
|
||||
assign LEDR[4] = \LEDR[4]~output_o ;
|
||||
|
||||
endmodule
|
||||
|
||||
module hard_block (
|
||||
|
||||
devpor,
|
||||
devclrn,
|
||||
devoe);
|
||||
|
||||
// Design Ports Information
|
||||
// ~ALTERA_TMS~ => Location: PIN_H2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_TCK~ => Location: PIN_G2, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_TDI~ => Location: PIN_L4, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_TDO~ => Location: PIN_M5, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// ~ALTERA_CONFIG_SEL~ => Location: PIN_H10, I/O Standard: 2.5 V, Current Strength: Default
|
||||
// ~ALTERA_nCONFIG~ => Location: PIN_H9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_nSTATUS~ => Location: PIN_G9, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
// ~ALTERA_CONF_DONE~ => Location: PIN_F8, I/O Standard: 2.5 V Schmitt Trigger, Current Strength: Default
|
||||
|
||||
input devpor;
|
||||
input devclrn;
|
||||
input devoe;
|
||||
|
||||
wire gnd;
|
||||
wire vcc;
|
||||
wire unknown;
|
||||
|
||||
assign gnd = 1'b0;
|
||||
assign vcc = 1'b1;
|
||||
assign unknown = 1'bx;
|
||||
|
||||
wire \~ALTERA_TMS~~padout ;
|
||||
wire \~ALTERA_TCK~~padout ;
|
||||
wire \~ALTERA_TDI~~padout ;
|
||||
wire \~ALTERA_CONFIG_SEL~~padout ;
|
||||
wire \~ALTERA_nCONFIG~~padout ;
|
||||
wire \~ALTERA_nSTATUS~~padout ;
|
||||
wire \~ALTERA_CONF_DONE~~padout ;
|
||||
wire \~ALTERA_TMS~~ibuf_o ;
|
||||
wire \~ALTERA_TCK~~ibuf_o ;
|
||||
wire \~ALTERA_TDI~~ibuf_o ;
|
||||
wire \~ALTERA_CONFIG_SEL~~ibuf_o ;
|
||||
wire \~ALTERA_nCONFIG~~ibuf_o ;
|
||||
wire \~ALTERA_nSTATUS~~ibuf_o ;
|
||||
wire \~ALTERA_CONF_DONE~~ibuf_o ;
|
||||
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,545 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel MegaCore Function License Agreement, or other
|
||||
applicable license agreement, including, without limitation,
|
||||
that your use is for the sole purpose of programming logic
|
||||
devices manufactured by Intel and sold by Intel or its
|
||||
authorized distributors. Please refer to the applicable
|
||||
agreement for further details.
|
||||
*/
|
||||
|
||||
HEADER
|
||||
{
|
||||
VERSION = 1;
|
||||
TIME_UNIT = ns;
|
||||
DATA_OFFSET = 0.0;
|
||||
DATA_DURATION = 1000.0;
|
||||
SIMULATION_TIME = 0.0;
|
||||
GRID_PHASE = 0.0;
|
||||
GRID_PERIOD = 10.0;
|
||||
GRID_DUTY_CYCLE = 50;
|
||||
}
|
||||
|
||||
SIGNAL("LEDR")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = BUS;
|
||||
WIDTH = 5;
|
||||
LSB_INDEX = 0;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[4]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[3]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[2]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[1]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[0]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("SW")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = BUS;
|
||||
WIDTH = 9;
|
||||
LSB_INDEX = 0;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("SW[8]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[7]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[6]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[5]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[4]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[3]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[2]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[1]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[0]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 480.0;
|
||||
LEVEL 1 FOR 520.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[8]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 480.0;
|
||||
LEVEL 1 FOR 520.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[7]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[6]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[5]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR";
|
||||
EXPAND_STATUS = EXPANDED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 0;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 1, 2, 3, 4, 5;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 1;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 2;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 3;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 4;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 5;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW";
|
||||
EXPAND_STATUS = EXPANDED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 6;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[8]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 7;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[7]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 8;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[6]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 9;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[5]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 10;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 11;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 12;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 13;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 14;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 15;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
TIME_BAR
|
||||
{
|
||||
TIME = 0;
|
||||
MASTER = TRUE;
|
||||
}
|
||||
;
|
||||
@ -0,0 +1,549 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
|
||||
HEADER
|
||||
{
|
||||
VERSION = 1;
|
||||
TIME_UNIT = ns;
|
||||
DATA_OFFSET = 0.0;
|
||||
DATA_DURATION = 1000.0;
|
||||
SIMULATION_TIME = 0.0;
|
||||
GRID_PHASE = 0.0;
|
||||
GRID_PERIOD = 10.0;
|
||||
GRID_DUTY_CYCLE = 50;
|
||||
}
|
||||
|
||||
SIGNAL("LEDR")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = BUS;
|
||||
WIDTH = 5;
|
||||
LSB_INDEX = 0;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[4]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[3]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[2]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[1]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("LEDR[0]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "LEDR";
|
||||
}
|
||||
|
||||
SIGNAL("SW")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = BUS;
|
||||
WIDTH = 9;
|
||||
LSB_INDEX = 0;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("SW[8]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[7]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[6]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[5]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[4]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[3]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[2]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[1]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
SIGNAL("SW[0]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "SW";
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 400.0;
|
||||
LEVEL 0 FOR 600.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("LEDR[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 400.0;
|
||||
LEVEL 0 FOR 600.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[8]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 400.0;
|
||||
LEVEL 0 FOR 600.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[7]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 400.0;
|
||||
LEVEL 0 FOR 600.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[6]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 400.0;
|
||||
LEVEL 0 FOR 600.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[5]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 1 FOR 400.0;
|
||||
LEVEL 0 FOR 600.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("SW[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR";
|
||||
EXPAND_STATUS = EXPANDED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 0;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 1, 2, 3, 4, 5;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 1;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 2;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 3;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 4;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "LEDR[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 5;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW";
|
||||
EXPAND_STATUS = EXPANDED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 6;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[8]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 7;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[7]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 8;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[6]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 9;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[5]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 10;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 11;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 12;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 13;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 14;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "SW[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 15;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
TIME_BAR
|
||||
{
|
||||
TIME = 0;
|
||||
MASTER = TRUE;
|
||||
}
|
||||
;
|
||||
@ -0,0 +1,44 @@
|
||||
vendor_name = ModelSim
|
||||
source_file = 1, C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/part3.v
|
||||
source_file = 1, C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform.vwf
|
||||
source_file = 1, C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf
|
||||
source_file = 1, Waveform2.vwf
|
||||
source_file = 1, Waveform3.vwf
|
||||
source_file = 1, Waveform4.vwf
|
||||
source_file = 1, C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/db/part3.cbx.xml
|
||||
design_name = part3
|
||||
instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, part3, 1
|
||||
instance = comp, \LEDR[0]~output , LEDR[0]~output, part3, 1
|
||||
instance = comp, \LEDR[1]~output , LEDR[1]~output, part3, 1
|
||||
instance = comp, \LEDR[2]~output , LEDR[2]~output, part3, 1
|
||||
instance = comp, \LEDR[3]~output , LEDR[3]~output, part3, 1
|
||||
instance = comp, \LEDR[4]~output , LEDR[4]~output, part3, 1
|
||||
instance = comp, \SW[4]~input , SW[4]~input, part3, 1
|
||||
instance = comp, \SW[0]~input , SW[0]~input, part3, 1
|
||||
instance = comp, \SW[8]~input , SW[8]~input, part3, 1
|
||||
instance = comp, \A0|x1 , A0|x1, part3, 1
|
||||
instance = comp, \SW[5]~input , SW[5]~input, part3, 1
|
||||
instance = comp, \SW[1]~input , SW[1]~input, part3, 1
|
||||
instance = comp, \A0|COUT~0 , A0|COUT~0, part3, 1
|
||||
instance = comp, \A1|x1 , A1|x1, part3, 1
|
||||
instance = comp, \SW[2]~input , SW[2]~input, part3, 1
|
||||
instance = comp, \SW[6]~input , SW[6]~input, part3, 1
|
||||
instance = comp, \A2|x0 , A2|x0, part3, 1
|
||||
instance = comp, \A2|x1 , A2|x1, part3, 1
|
||||
instance = comp, \A2|COUT~2 , A2|COUT~2, part3, 1
|
||||
instance = comp, \A2|COUT~3 , A2|COUT~3, part3, 1
|
||||
instance = comp, \SW[3]~input , SW[3]~input, part3, 1
|
||||
instance = comp, \SW[7]~input , SW[7]~input, part3, 1
|
||||
instance = comp, \A3|x1 , A3|x1, part3, 1
|
||||
instance = comp, \A3|COUT~0 , A3|COUT~0, part3, 1
|
||||
instance = comp, \~QUARTUS_CREATED_UNVM~ , ~QUARTUS_CREATED_UNVM~, part3, 1
|
||||
instance = comp, \~QUARTUS_CREATED_ADC1~ , ~QUARTUS_CREATED_ADC1~, part3, 1
|
||||
instance = comp, \~QUARTUS_CREATED_ADC2~ , ~QUARTUS_CREATED_ADC2~, part3, 1
|
||||
design_name = hard_block
|
||||
instance = comp, \~ALTERA_TMS~~ibuf , ~ALTERA_TMS~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_TCK~~ibuf , ~ALTERA_TCK~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_TDI~~ibuf , ~ALTERA_TDI~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_CONFIG_SEL~~ibuf , ~ALTERA_CONFIG_SEL~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_nCONFIG~~ibuf , ~ALTERA_nCONFIG~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_nSTATUS~~ibuf , ~ALTERA_nSTATUS~~ibuf, hard_block, 1
|
||||
instance = comp, \~ALTERA_CONF_DONE~~ibuf , ~ALTERA_CONF_DONE~~ibuf, hard_block, 1
|
||||
42
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/transcript
Normal file
42
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/transcript
Normal file
@ -0,0 +1,42 @@
|
||||
# do part3.do
|
||||
# ** Warning: (vlib-34) Library already exists at "work".
|
||||
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
||||
# Start time: 00:52:03 on Apr 25,2021
|
||||
# vlog -work work part3.vo
|
||||
# -- Compiling module part3
|
||||
# -- Compiling module hard_block
|
||||
#
|
||||
# Top level modules:
|
||||
# part3
|
||||
# End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
||||
# Start time: 00:52:03 on Apr 25,2021
|
||||
# vlog -work work Waveform1.vwf.vt
|
||||
# -- Compiling module part3_vlg_vec_tst
|
||||
#
|
||||
# Top level modules:
|
||||
# part3_vlg_vec_tst
|
||||
# End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# vsim -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst
|
||||
# Start time: 00:52:03 on Apr 25,2021
|
||||
# Loading work.part3_vlg_vec_tst
|
||||
# Loading work.part3
|
||||
# Loading work.hard_block
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_lcell_comb
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_io_obuf
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_io_ibuf
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_unvm
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_adcblock
|
||||
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC1~ '. Expected 8, found 7.
|
||||
# Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: part3.vo Line: 481
|
||||
# ** Warning: (vsim-3722) part3.vo(481): [TFMPC] - Missing connection for port 'clk_dft'.
|
||||
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC2~ '. Expected 8, found 7.
|
||||
# Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: part3.vo Line: 504
|
||||
# ** Warning: (vsim-3722) part3.vo(504): [TFMPC] - Missing connection for port 'clk_dft'.
|
||||
# after#26
|
||||
# ** Note: $finish : Waveform1.vwf.vt(45)
|
||||
# Time: 1 us Iteration: 0 Instance: /part3_vlg_vec_tst
|
||||
# End time: 00:52:04 on Apr 25,2021, Elapsed time: 0:00:01
|
||||
# Errors: 0, Warnings: 4
|
||||
403
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/vwf_sim_transcript
Normal file
403
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/vwf_sim_transcript
Normal file
@ -0,0 +1,403 @@
|
||||
Determining the location of the ModelSim executable...
|
||||
|
||||
Using: c:/intelfpga_lite/20.1/modelsim_ase/win32aloem/
|
||||
|
||||
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
|
||||
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
|
||||
|
||||
**** Generating the ModelSim Testbench ****
|
||||
|
||||
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt"
|
||||
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime EDA Netlist Writer
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Info: Your use of Intel Corporation's design tools, logic functions
|
||||
Info: and other software and tools, and any partner logic
|
||||
Info: functions, and any output files from any of the foregoing
|
||||
Info: (including device programming or simulation files), and any
|
||||
Info: associated documentation or information are expressly subject
|
||||
Info: to the terms and conditions of the Intel Program License
|
||||
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
Info: the Intel FPGA IP License Agreement, or other applicable license
|
||||
Info: agreement, including, without limitation, that your use is for
|
||||
Info: the sole purpose of programming logic devices manufactured by
|
||||
Info: Intel and sold by Intel or its authorized distributors. Please
|
||||
Info: refer to the applicable agreement for further details, at
|
||||
Info: https://fpgasoftware.intel.com/eula.
|
||||
Info: Processing started: Sun Apr 25 00:51:58 2021
|
||||
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off part3 -c part3 --vector_source="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf" --testbench_file="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/Waveform1.vwf.vt"
|
||||
Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored
|
||||
Warning
|
||||
(20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
|
||||
utput pin "LEDR" in vector source file when writing test bench files
|
||||
|
||||
Completed successfully.
|
||||
|
||||
Completed successfully.
|
||||
|
||||
**** Generating the functional simulation netlist ****
|
||||
|
||||
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3
|
||||
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime EDA Netlist Writer
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Info: Your use of Intel Corporation's design tools, logic functions
|
||||
Info: and other software and tools, and any partner logic
|
||||
Info: functions, and any output files from any of the foregoing
|
||||
Info: (including device programming or simulation files), and any
|
||||
Info: associated documentation or information are expressly subject
|
||||
Info: to the terms and conditions of the Intel Program License
|
||||
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
Info: the Intel FPGA IP License Agreement, or other applicable license
|
||||
Info: agreement, including, without limitation, that your use is for
|
||||
Info: the sole purpose of programming logic devices manufactured by
|
||||
Info: Intel and sold by Intel or its authorized distributors. Please
|
||||
Info: refer to the applicable agreement for further details, at
|
||||
Info: https://fpgasoftware.intel.com/eula.
|
||||
Info: Processing started: Sun Apr 25 00:52:00 2021
|
||||
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/" part3 -c part3
|
||||
Warning (20013): Ignored 24 assignments for entity "Lab1Pt1" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity Lab1Pt1 -section_id Top was ignored
|
||||
Warning (20013): Ignored 24 assignments for entity "part1" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1 -section_id Top was ignored
|
||||
Warning (20013): Ignored 24 assignments for entity "part1_bcd" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part1_bcd -section_id Top was ignored
|
||||
Warning (20013): Ignored 24 assignments for entity "part4" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part4 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE
|
||||
_STRICT_PRESERVATION OFF -entity part4 -section_id Top was ignored
|
||||
Warning (20013): Ignored 24 assignments for entity "part5" -- entity does not exist in design
|
||||
Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity part5 -section_id Top was ignored
|
||||
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity part5 -section_id Top was ignored
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (204019): Generated file part3.vo in folder "C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee
|
||||
/Lab2/part3/simulation/qsim//" for EDA simulation tool
|
||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 126 warnings
|
||||
Info: Peak virtual memory: 4660 megabytes
|
||||
Info: Processing ended: Sun Apr 25 00:52:01 2021
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
Completed successfully.
|
||||
|
||||
**** Generating the ModelSim .do script ****
|
||||
|
||||
C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/part3.do generated.
|
||||
|
||||
Completed successfully.
|
||||
|
||||
**** Running the ModelSim simulation ****
|
||||
|
||||
c:/intelfpga_lite/20.1/modelsim_ase/win32aloem//vsim -c -do part3.do
|
||||
|
||||
Reading pref.tcl
|
||||
|
||||
# 2020.1
|
||||
|
||||
|
||||
# do part3.do
|
||||
|
||||
# ** Warning: (vlib-34) Library already exists at "work".
|
||||
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
||||
# Start time: 00:52:03 on Apr 25,2021
|
||||
# vlog -work work part3.vo
|
||||
|
||||
# -- Compiling module part3
|
||||
# -- Compiling module hard_block
|
||||
#
|
||||
# Top level modules:
|
||||
# part3
|
||||
# End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
|
||||
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
||||
# Start time: 00:52:03 on Apr 25,2021
|
||||
# vlog -work work Waveform1.vwf.vt
|
||||
# -- Compiling module part3_vlg_vec_tst
|
||||
#
|
||||
# Top level modules:
|
||||
# part3_vlg_vec_tst
|
||||
# End time: 00:52:03 on Apr 25,2021, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
|
||||
# vsim -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.part3_vlg_vec_tst
|
||||
# Start time: 00:52:03 on Apr 25,2021
|
||||
# Loading work.part3_vlg_vec_tst
|
||||
# Loading work.part3
|
||||
# Loading work.hard_block
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_lcell_comb
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_io_obuf
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_io_ibuf
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_unvm
|
||||
# Loading fiftyfivenm_ver.fiftyfivenm_adcblock
|
||||
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC1~ '. Expected 8, found 7.
|
||||
# Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC1~ File: part3.vo Line: 481
|
||||
# ** Warning: (vsim-3722) part3.vo(481): [TFMPC] - Missing connection for port 'clk_dft'.
|
||||
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '\~QUARTUS_CREATED_ADC2~ '. Expected 8, found 7.
|
||||
# Time: 0 ps Iteration: 0 Instance: /part3_vlg_vec_tst/i1/\~QUARTUS_CREATED_ADC2~ File: part3.vo Line: 504
|
||||
# ** Warning: (vsim-3722) part3.vo(504): [TFMPC] - Missing connection for port 'clk_dft'.
|
||||
# after#26
|
||||
# ** Note: $finish : Waveform1.vwf.vt(45)
|
||||
# Time: 1 us Iteration: 0 Instance: /part3_vlg_vec_tst
|
||||
# End time: 00:52:04 on Apr 25,2021, Elapsed time: 0:00:01
|
||||
# Errors: 0, Warnings: 4
|
||||
|
||||
Completed successfully.
|
||||
|
||||
**** Converting ModelSim VCD to vector waveform ****
|
||||
|
||||
Reading C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/Waveform1.vwf...
|
||||
|
||||
Reading C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/part3.msim.vcd...
|
||||
|
||||
Processing channel transitions...
|
||||
|
||||
Writing the resulting VWF to C:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim/part3_20210425005204.sim.vwf
|
||||
|
||||
Finished VCD to VWF conversion.
|
||||
|
||||
Completed successfully.
|
||||
|
||||
All completed.
|
||||
80
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_info
Normal file
80
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_info
Normal file
@ -0,0 +1,80 @@
|
||||
m255
|
||||
K4
|
||||
z2
|
||||
!s11f vlog 2020.1 2020.02, Feb 28 2020
|
||||
13
|
||||
!s112 1.1
|
||||
!i10d 8192
|
||||
!i10e 25
|
||||
!i10f 100
|
||||
cModel Technology
|
||||
Z0 dC:/Users/ANDREW/UAH/SP2021/EE203/Projects/Noah Woodlee/Lab2/part3/simulation/qsim
|
||||
vhard_block
|
||||
Z1 !s110 1619329923
|
||||
!i10b 1
|
||||
!s100 hk;iOES1OEEkmIH`g28P^2
|
||||
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
|
||||
I:0VO>2Okd0fffWJm?T;9Q0
|
||||
Z3 VDg1SIo80bB@j0V0VzS_@n1
|
||||
R0
|
||||
Z4 w1619329921
|
||||
Z5 8part3.vo
|
||||
Z6 Fpart3.vo
|
||||
!i122 2
|
||||
L0 538 45
|
||||
Z7 OV;L;2020.1;71
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z8 !s108 1619329923.000000
|
||||
Z9 !s107 part3.vo|
|
||||
Z10 !s90 -work|work|part3.vo|
|
||||
!i113 1
|
||||
Z11 o-work work
|
||||
Z12 tCvgOpt 0
|
||||
vpart3
|
||||
R1
|
||||
!i10b 1
|
||||
!s100 @Dk8V0jGN0cVf@O6]8BlI1
|
||||
R2
|
||||
IN0IA31^WL4mZlO5c]]QzO1
|
||||
R3
|
||||
R0
|
||||
R4
|
||||
R5
|
||||
R6
|
||||
!i122 2
|
||||
L0 32 505
|
||||
R7
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R8
|
||||
R9
|
||||
R10
|
||||
!i113 1
|
||||
R11
|
||||
R12
|
||||
vpart3_vlg_vec_tst
|
||||
R1
|
||||
!i10b 1
|
||||
!s100 fT[cU72ZYER_eYz1VlYE[2
|
||||
R2
|
||||
IK`ig?Wo_giD0?]E<@Be_53
|
||||
R3
|
||||
R0
|
||||
w1619329920
|
||||
8Waveform1.vwf.vt
|
||||
FWaveform1.vwf.vt
|
||||
!i122 3
|
||||
L0 30 67
|
||||
R7
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R8
|
||||
!s107 Waveform1.vwf.vt|
|
||||
!s90 -work|work|Waveform1.vwf.vt|
|
||||
!i113 1
|
||||
R11
|
||||
R12
|
||||
BIN
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib.qdb
Normal file
BIN
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib.qdb
Normal file
Binary file not shown.
BIN
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qdb
Normal file
BIN
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qdb
Normal file
Binary file not shown.
BIN
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qpg
Normal file
BIN
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qpg
Normal file
Binary file not shown.
BIN
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qtl
Normal file
BIN
EE203/Noah Woodlee/Lab2/part3/simulation/qsim/work/_lib1_0.qtl
Normal file
Binary file not shown.
@ -0,0 +1,4 @@
|
||||
m255
|
||||
K4
|
||||
z0
|
||||
cModel Technology
|
||||
Reference in New Issue
Block a user